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all: Fix spelling mistakes based on codespell check.

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Signed-off-by: Damien George <damien@micropython.org>
This commit is contained in:
Damien George
2023-03-08 14:10:02 +11:00
parent e160fe7bc6
commit b1229efbd1
191 changed files with 282 additions and 282 deletions
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6
ports/samd/mcu/samd51/clock_config.c
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@@ -172,11 +172,11 @@ void check_usb_recovery_mode(void) {
// not exactly 48Mhz and has a substantional temperature drift.
//
// If MICROPY_HW_DFLL_USB_SYNC = 1, the DFLL48 is synchronized with the 1 kHz USB sync
// signal. If after boot there is no USB sync withing 500ms, the configuratuion falls
// signal. If after boot there is no USB sync within 500ms, the configuration falls
// back to a free running 48Mhz oscillator.
//
// In all modes, the 48MHz signal has a substantial jitter, largest when
// MICROPY_HW_DFLL_USB_SYNC is active. That is caused by the repective
// MICROPY_HW_DFLL_USB_SYNC is active. That is caused by the respective
// reference frequencies of 32kHz or 1 kHz being low. That affects most
// PWM. Std Dev at 1kHz 0.156Hz (w. Crystal) up to 0.4 Hz (with USB sync).
//
@@ -195,7 +195,7 @@ void init_clocks(uint32_t cpu_freq) {
// GCLK4: 32kHz, source: XOSC32K, if crystal present, usage: DFLL48M reference
// GCLK5: 48MHz, source: DFLL48M, usage: USB
// DFLL48M: Reference sources:
// - in closed loop mode: eiter XOSC32K or OSCULP32K or USB clock
// - in closed loop mode: either XOSC32K or OSCULP32K or USB clock
// - in open loop mode: None
// DPLL0: 48 - 200 MHz