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samd/clock_config: Set up the clock configuration.

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Clock settings:
- GCLK0: 48 MHz (SAMD21) or 120 MHz(SAMD51).
- GCLK1: 32768 Hz for driving the PLL.
- GCLK2: 48 MHz for tzhe peripheral clock.
- GCLK3: 1 MHz (SAMD21) or 8 MHz (SAMD51) for the µs ticks timer.
- GCLK8: 1 kHz for WDT (SAMD21 only).

If a 32 kHz crystal is present, it will be used as clock source.  Otherwise
the DFLL48M in open-loop mode is used.

GCLK0 for SAM51 can be changed between 48 MHz and 200 MHz.  The specified
range is 96 MHz - 120 MHz.
This commit is contained in:
robert-hh
2022-06-04 16:31:46 +02:00
committed by Damien George
parent 949a808076
commit b4d29fd47a
5 changed files with 431 additions and 28 deletions
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11
ports/samd/samd_soc.h
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@@ -28,6 +28,7 @@
#include <stdint.h>
#include "sam.h"
#include "clock_config.h"
void samd_init(void);
void samd_main(void);
@@ -38,4 +39,14 @@ void USB_1_Handler_wrapper(void);
void USB_2_Handler_wrapper(void);
void USB_3_Handler_wrapper(void);
void common_uart_irq_handler(int uart_nr);
void common_spi_irq_handler(int spi_nr);
void common_i2c_irq_handler(int i2c_nr);
void sercom_enable(Sercom *spi, int state);
void sercom_register_irq(int sercom_id, int mode);
#define SERCOM_IRQ_TYPE_UART (0)
#define SERCOM_IRQ_TYPE_SPI (1)
#define SERCOM_IRQ_TYPE_I2C (2)
#endif // MICROPY_INCLUDED_SAMD_SAMD_SOC_H