From fda9bf491767603b762926fde35325480b5b14ee Mon Sep 17 00:00:00 2001 From: Alessandro Gatti Date: Sat, 22 Mar 2025 02:40:59 +0100 Subject: [PATCH] esp32/esp32_common.cmake: Clean up RISC-V directives. This commit cleans up a couple of RISC-V specific directives in the build script. Namely, removes the forced inclusion of the "riscv" component and introduces proper mpy-cross flags. The "riscv" component is already included by the ESP-IDF build framework, as certain low-level components would not build otherwise, so there is no need to add it to the required components list. The architecture flag for mpy-cross is now set for RISC-V targets, as it was previously set only for Xtensa targets (and it relied on a string comparison rather than using the appropriate configuration variable). Signed-off-by: Alessandro Gatti --- ports/esp32/esp32_common.cmake | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/ports/esp32/esp32_common.cmake b/ports/esp32/esp32_common.cmake index d026a64b0c..99fcebac32 100644 --- a/ports/esp32/esp32_common.cmake +++ b/ports/esp32/esp32_common.cmake @@ -20,7 +20,6 @@ if(CONFIG_IDF_TARGET_ARCH_RISCV) ${MICROPY_DIR}/shared/runtime/gchelper_native.c ${MICROPY_DIR}/shared/runtime/gchelper_rv32i.s ) - list(APPEND IDF_COMPONENTS riscv) endif() if(NOT DEFINED MICROPY_PY_TINYUSB) @@ -237,8 +236,10 @@ idf_component_register( set(MICROPY_TARGET ${COMPONENT_TARGET}) # Define mpy-cross flags, for use with frozen code. -if(CONFIG_IDF_TARGET_ARCH STREQUAL "xtensa") -set(MICROPY_CROSS_FLAGS -march=xtensawin) +if(CONFIG_IDF_TARGET_ARCH_XTENSA) + set(MICROPY_CROSS_FLAGS -march=xtensawin) +elseif(CONFIG_IDF_TARGET_ARCH_RISCV) + set(MICROPY_CROSS_FLAGS -march=rv32imc) endif() # Set compile options for this port.