This commit adds support for writing inline assembler functions when
targeting a RV32IMC processor.
Given that this takes up a bit of rodata space due to its large
instruction decoding table and its extensive error messages, it is
enabled by default only on offline targets such as mpy-cross and the
qemu port.
Signed-off-by: Alessandro Gatti <a.gatti@frob.it>
The RV32 emitter always scheduled short jumps even outside the emit
compiler pass. Running the full test suite through the native emitter
instead of just the tests that depend on the emitter at runtime (as in,
`micropython/native_*` and `micropython/viper_* tests`) uncovered more
places where the invalid behaviour was still present.
Signed-off-by: Alessandro Gatti <a.gatti@frob.it>
As per discussion in #15347, non-standard binary literals have been
removed in favour of their hexadecimal counterparts.
Signed-off-by: Alessandro Gatti <a.gatti@frob.it>
This commit changes a few code sequences to use more compressed opcodes
where possible. The sequences in question are the ones that show up the
most in the test suite and require the least amount of code changes, namely
short offset loads from memory to RET/ARG registers, indirect calls through
the function table, register-based jumps, locals' offset calculation,
reg-is-null jumps, and register comparisons.
There are no speed losses or gains from these changes, but there is an
average 15-20% generated code size reduction.
Signed-off-by: Alessandro Gatti <a.gatti@frob.it>
This adds a native code generation backend for RISC-V RV32I CPUs, currently
limited to the I, M, and C instruction sets.
Signed-off-by: Alessandro Gatti <a.gatti@frob.it>
