This commit minimises the amount of code required to perform validation
of load/store opcodes, streamlining their validation and serialisation.
Load/store opcodes used to be handled as a special case due to how its
peculiar syntax yields parse node arguments that cannot be handled by
the regular validation and serialisation functions.
The changes in this commit attempt to reduce the amount of special code
needed for those opcodes to its bare minimum, by removing the special
opcode handling step, merging the validation and serialisation pass for
the combined offset + base register operand, and integrate said changes
in the existing argument handling structure.
That allowed to rework the special operand parsing function to make it
smaller, and remove the code that performed the special case validation
and emitted the opcode.
Signed-off-by: Alessandro Gatti <a.gatti@frob.it>
This commit simplifies the way arguments are validated when processing
RV32 inline assembler opcodes.
Opcode arguments were handled in two separate passes, one that performed
a pure validation (with an early rejection in case of errors), and
another that converted the parse node into a serialised value but
without any error checking.
Considering that the validation pass effectively performed the parse
node conversion and then discarded its result once validated, it is
preferable to hold onto the serialised result to reuse it later at
opcode generation time.
With these changes, those two passes are merged into one single
operation when applicable (basically any opcode that doesn't use an
integer offset), removing a fair amount of duplicate code. The size
savings should be around half a kilobyte, with no other changes in the
assembler's behaviour.
Signed-off-by: Alessandro Gatti <a.gatti@frob.it>
This commit adds support for Zba opcodes to the RV32 inline assembler.
Three new opcodes were added, SH1ADD, SH2ADD, and SH3ADD, which performs
a scaled addition (by 1, 2, or 3 bits respectively). At the moment only
qemu's VIRT_RV32 and rp2's RPI_PICO2/RPI_PICO2_W ports support these
opcodes (the latter only when using the RISCV variant).
Signed-off-by: Alessandro Gatti <a.gatti@frob.it>
Otherwise, when compiling on 16-bit systems (where `mp_uint_t` is 16 bits
wide) the compiler warns about "left shift count >= width of type", from
the static inline functions that have RV32_ENCODE_TYPE_xxx macros which
do a lot of bit shifting.
Signed-off-by: Damien George <damien@micropython.org>
This commit introduces a few changes aimed at reducing the amount of
space taken by the inline assembler once compiled:
* The register string table uses 2 bytes for each qstr rather than the
usual 4
* The opcode table uses 2 bytes for each qstr rather than the usual 4
* Opcode masks are not embedded in each opcode entry but looked up via
an additional smaller table, reducing the number of bytes taken by
an opcode's masks from 12 to 2 (with a fixed overhead of 24 bytes for
the the masks themselves stored elsewhere)
* Some error messages had a trailing period, now removed
* Error messages have been parameterised when possible, and the overall
text length is smaller.
Signed-off-by: Alessandro Gatti <a.gatti@frob.it>
This commit fixes a compilation warning (turned error) about a
potentially uninitialised variable being used. The warning can be
ignored as the variable in question is always written to, but the code
has been changed to silence that warning.
Signed-off-by: Alessandro Gatti <a.gatti@frob.it>
This commit adds support for writing inline assembler functions when
targeting a RV32IMC processor.
Given that this takes up a bit of rodata space due to its large
instruction decoding table and its extensive error messages, it is
enabled by default only on offline targets such as mpy-cross and the
qemu port.
Signed-off-by: Alessandro Gatti <a.gatti@frob.it>
