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2 Commits
| Author | SHA1 | Message | Date | |
|---|---|---|---|---|
Alessandro Gatti
|
9dcad25de6 |
py/emitinlinextensa: Add inline assembler support for windowed cores.
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This commit introduces support for writing inline assembler code snippets when targeting Xtensa cores that use register windows (eg. the whole ESP32 family). Opcodes support is still limited to what the ESP8266 supports (as in, LX3 cores opcodes), however each LX core version is guaranteed to support all previous versions' opcodes as well. The ESP32 does not have the inline assembler enabled by default, following the existing expectations when it comes to firmware footprint. Since now emitted functions may have one of two possible exit sequences, the L32I test had to be fixed. It would return the word containing the L32I opcode itself, but the upper 8 bits of the word came from the following opcode - which can change depending on the exit code sequence. Signed-off-by: Alessandro Gatti <a.gatti@frob.it> |
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Alessandro Gatti
|
1006ed69f0 |
py/emitinlinextensa: Add the rest of LX3 opcodes to the assembler.
This commit expands the Xtensa inline assembler to support most if not all opcodes available on the ESP8266 and LX3 Xtensa cores. This is meant as a stepping stone to add inline assembler support for the ESP32 and its LX6 core, along to windowed-specific opcodes and additional opcodes that are present only on the LX7 core (ESP32-S3 and later). New opcodes being added are covered by tests, and the provided tests were expanded to also include opcodes available in the existing implementation. Given that the ESP8266 space requirements are tighter than ESP32's, certain opcodes that won't be commonly used have been put behind a define to save some space in the general use case. Signed-off-by: Alessandro Gatti <a.gatti@frob.it> |