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fe32e1d3a1
Not currently building, and too many versions to concurrently support. This work was funded through GitHub Sponsors. Signed-off-by: Angus Gratton <angus@redyak.com.au>
183 lines
6.1 KiB
C
183 lines
6.1 KiB
C
/*
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* This file is part of the MicroPython project, http://micropython.org/
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*
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* The MIT License (MIT)
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*
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* Copyright (c) 2021 Jim Mussared
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "py/mpconfig.h"
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#include "py/mphal.h"
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#include "modesp32.h"
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#include "rom/gpio.h"
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#include "soc/gpio_reg.h"
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#include "soc/gpio_sig_map.h"
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#if MICROPY_PY_MACHINE_BITSTREAM
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/******************************************************************************/
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// Bit-bang implementation
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#define NS_TICKS_OVERHEAD (6)
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// This is a translation of the cycle counter implementation in ports/stm32/machine_bitstream.c.
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static void IRAM_ATTR machine_bitstream_high_low_bitbang(mp_hal_pin_obj_t pin, uint32_t *timing_ns, const uint8_t *buf, size_t len) {
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uint32_t pin_mask, gpio_reg_set, gpio_reg_clear;
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#if SOC_GPIO_PIN_COUNT > 32
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if (pin >= 32) {
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pin_mask = 1 << (pin - 32);
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gpio_reg_set = GPIO_OUT1_W1TS_REG;
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gpio_reg_clear = GPIO_OUT1_W1TC_REG;
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} else
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#endif
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{
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pin_mask = 1 << pin;
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gpio_reg_set = GPIO_OUT_W1TS_REG;
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gpio_reg_clear = GPIO_OUT_W1TC_REG;
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}
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// Convert ns to cpu ticks [high_time_0, period_0, high_time_1, period_1].
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uint32_t fcpu_mhz = esp_rom_get_cpu_ticks_per_us();
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for (size_t i = 0; i < 4; ++i) {
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timing_ns[i] = fcpu_mhz * timing_ns[i] / 1000;
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if (timing_ns[i] > NS_TICKS_OVERHEAD) {
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timing_ns[i] -= NS_TICKS_OVERHEAD;
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}
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if (i % 2 == 1) {
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// Convert low_time to period (i.e. add high_time).
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timing_ns[i] += timing_ns[i - 1];
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}
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}
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uint32_t irq_state = mp_hal_quiet_timing_enter();
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for (size_t i = 0; i < len; ++i) {
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uint8_t b = buf[i];
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for (size_t j = 0; j < 8; ++j) {
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GPIO_REG_WRITE(gpio_reg_set, pin_mask);
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uint32_t start_ticks = mp_hal_ticks_cpu();
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uint32_t *t = &timing_ns[b >> 6 & 2];
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while (mp_hal_ticks_cpu() - start_ticks < t[0]) {
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;
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}
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GPIO_REG_WRITE(gpio_reg_clear, pin_mask);
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b <<= 1;
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while (mp_hal_ticks_cpu() - start_ticks < t[1]) {
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;
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}
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}
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}
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mp_hal_quiet_timing_exit(irq_state);
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}
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#if SOC_RMT_SUPPORTED
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/******************************************************************************/
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// RMT implementation
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#include "driver/rmt_tx.h"
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#include "driver/rmt_encoder.h"
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static bool machine_bitstream_high_low_rmt(mp_hal_pin_obj_t pin, uint32_t *timing_ns, const uint8_t *buf, size_t len) {
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// Use 40MHz clock (although 2MHz would probably be sufficient).
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uint32_t clock_div = 2;
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rmt_channel_handle_t channel = NULL;
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rmt_tx_channel_config_t tx_chan_config = {
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.clk_src = RMT_CLK_SRC_DEFAULT,
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.gpio_num = pin,
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.mem_block_symbols = SOC_RMT_MEM_WORDS_PER_CHANNEL,
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.resolution_hz = APB_CLK_FREQ / clock_div,
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.trans_queue_depth = 1,
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};
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if (rmt_new_tx_channel(&tx_chan_config, &channel) != ESP_OK) {
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return false;
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}
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check_esp_err(rmt_enable(channel));
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// Get the tick rate in kHz (this will likely be 40000).
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uint32_t counter_clk_khz = APB_CLK_FREQ / clock_div;
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counter_clk_khz /= 1000;
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// Convert nanoseconds to pulse duration.
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// Example: 500ns = 40000 * 500 / 1e6 = 20 ticks
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// 20 ticks / 40MHz = 500e-9
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rmt_bytes_encoder_config_t bytes_encoder_config = {
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.bit0 = {
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.level0 = 1,
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.duration0 = (counter_clk_khz * timing_ns[0]) / 1e6,
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.level1 = 0,
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.duration1 = (counter_clk_khz * timing_ns[1]) / 1e6,
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},
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.bit1 = {
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.level0 = 1,
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.duration0 = (counter_clk_khz * timing_ns[2]) / 1e6,
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.level1 = 0,
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.duration1 = (counter_clk_khz * timing_ns[3]) / 1e6,
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},
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.flags.msb_first = 1
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};
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// Install the bits->highlow encoder.
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rmt_encoder_handle_t encoder;
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check_esp_err(rmt_new_bytes_encoder(&bytes_encoder_config, &encoder));
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rmt_transmit_config_t tx_config = {
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.loop_count = 0,
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.flags.eot_level = 0,
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};
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// Stream the byte data using the encoder.
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rmt_encoder_reset(encoder);
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check_esp_err(rmt_transmit(channel, encoder, buf, len, &tx_config));
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// Wait until completion.
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rmt_tx_wait_all_done(channel, -1);
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// Disable and release channel.
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check_esp_err(rmt_del_encoder(encoder));
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rmt_disable(channel);
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rmt_del_channel(channel);
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// Cancel RMT output to GPIO pin.
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esp_rom_gpio_connect_out_signal(pin, SIG_GPIO_OUT_IDX, false, false);
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return true;
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}
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#endif // SOC_RMT_SUPPORTED
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/******************************************************************************/
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// Interface to machine.bitstream
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void machine_bitstream_high_low(mp_hal_pin_obj_t pin, uint32_t *timing_ns, const uint8_t *buf, size_t len) {
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#if SOC_RMT_SUPPORTED
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if (esp32_rmt_bitstream_enabled && machine_bitstream_high_low_rmt(pin, timing_ns, buf, len)) {
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// Use of RMT was successful.
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return;
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}
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#endif
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machine_bitstream_high_low_bitbang(pin, timing_ns, buf, len);
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}
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#endif // MICROPY_PY_MACHINE_BITSTREAM
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