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94 lines
4.0 KiB
C
94 lines
4.0 KiB
C
/*
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* This file is part of the MicroPython project, http://micropython.org/
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*
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* The MIT License (MIT)
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*
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* Copyright (c) 2013-2023 Damien P. George
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* Copyright (c) 2024 OpenMV LLC.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#ifndef MICROPY_INCLUDED_ALIF_IRQ_H
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#define MICROPY_INCLUDED_ALIF_IRQ_H
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#include <stdint.h>
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#include ALIF_CMSIS_H
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// IRQ priority definitions.
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//
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// The M55-HP CPU has __NVIC_PRIO_BITS==8 bits for setting the IRQ priority.
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// It uses NVIC_SetPriorityGrouping(0) which is 7 bits for preempt priority
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// and 1 bit for the sub-priority.
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//
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// Lower number implies higher interrupt priority.
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#define NVIC_PRIORITYGROUP_7 ((uint32_t)0x00000000U)
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#define IRQ_PRI_SYSTEM_TICK NVIC_EncodePriority(NVIC_PRIORITYGROUP_7, 0, 0)
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#define IRQ_PRI_MHU NVIC_EncodePriority(NVIC_PRIORITYGROUP_7, 0, 0)
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#define IRQ_PRI_QUIET_TIMING NVIC_EncodePriority(NVIC_PRIORITYGROUP_7, 1, 0)
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#define IRQ_PRI_UART_REPL NVIC_EncodePriority(NVIC_PRIORITYGROUP_7, 1, 0)
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#define IRQ_PRI_ADC NVIC_EncodePriority(NVIC_PRIORITYGROUP_7, 3, 0)
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#define IRQ_PRI_CSI NVIC_EncodePriority(NVIC_PRIORITYGROUP_7, 5, 0)
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#define IRQ_PRI_USB NVIC_EncodePriority(NVIC_PRIORITYGROUP_7, 7, 0)
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#define IRQ_PRI_HWSEM NVIC_EncodePriority(NVIC_PRIORITYGROUP_7, 8, 0)
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#define IRQ_PRI_GPU NVIC_EncodePriority(NVIC_PRIORITYGROUP_7, 10, 0)
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#define IRQ_PRI_GPIO NVIC_EncodePriority(NVIC_PRIORITYGROUP_7, 50, 0)
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#define IRQ_PRI_I2C NVIC_EncodePriority(NVIC_PRIORITYGROUP_7, 60, 0)
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#define IRQ_PRI_RTC NVIC_EncodePriority(NVIC_PRIORITYGROUP_7, 100, 0)
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#define IRQ_PRI_CYW43 NVIC_EncodePriority(NVIC_PRIORITYGROUP_7, 126, 0)
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#define IRQ_PRI_PENDSV NVIC_EncodePriority(NVIC_PRIORITYGROUP_7, 127, 0)
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// these states correspond to values from query_irq, enable_irq and disable_irq
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#define IRQ_STATE_DISABLED (0x00000001)
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#define IRQ_STATE_ENABLED (0x00000000)
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static inline uint32_t query_irq(void) {
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return __get_PRIMASK();
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}
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static inline void enable_irq(uint32_t state) {
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__set_PRIMASK(state);
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}
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static inline uint32_t disable_irq(void) {
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uint32_t state = __get_PRIMASK();
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__disable_irq();
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return state;
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}
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// irqs with a priority value greater or equal to "pri" will be disabled
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static inline uint32_t raise_irq_pri(uint32_t pri) {
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uint32_t basepri = __get_BASEPRI();
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// If non-zero, the processor does not process any exception with a
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// priority value greater than or equal to BASEPRI.
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// When writing to BASEPRI_MAX the write goes to BASEPRI only if either:
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// - Rn is non-zero and the current BASEPRI value is 0
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// - Rn is non-zero and less than the current BASEPRI value
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pri <<= (8 - __NVIC_PRIO_BITS);
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__ASM volatile ("msr basepri_max, %0" : : "r" (pri) : "memory");
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return basepri;
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}
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// "basepri" should be the value returned from raise_irq_pri
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static inline void restore_irq_pri(uint32_t basepri) {
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__set_BASEPRI(basepri);
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}
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#endif // MICROPY_INCLUDED_ALIF_IRQ_H
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