mirror of
https://github.com/micropython/micropython.git
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481 lines
17 KiB
C
481 lines
17 KiB
C
/*
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* This file is part of the MicroPython project, http://micropython.org/
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*
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* The MIT License (MIT)
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*
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* Copyright (c) 2024 OpenMV LLC.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "py/mperrno.h"
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#include "py/mphal.h"
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#if MICROPY_HW_ENABLE_OSPI
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#include "ospi_ext.h"
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#include "ospi_flash.h"
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#include "ospi_drv.h"
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#include "ospi_xip_user.h"
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#include "pinconf.h"
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#define WAIT_SR_TIMEOUT (1000000)
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// Generic SPI flash commands.
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#define CMD_SPI_WREN (0x06)
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// This is the maximum number of bytes that can be written to SPI flash at once.
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#define PAGE_SIZE (256)
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// All OSP0/OSPI1 pins use the same alternate function.
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#define OSPI_PIN_FUNCTION PINMUX_ALTERNATE_FUNCTION_1
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typedef struct _ospi_flash_t {
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const ospi_pin_settings_t *pin;
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const ospi_flash_settings_t *set;
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ospi_flash_cfg_t cfg;
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bool xip_active;
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} ospi_flash_t;
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static ospi_flash_t global_flash;
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/******************************************************************************/
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// Generic SPI-flash helper functions.
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static void ospi_flash_wren_spi(ospi_flash_t *self) {
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uint8_t buf[1] = {CMD_SPI_WREN};
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ospi_spi_transfer(&self->cfg, 1, buf, buf);
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}
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static int ospi_flash_read_cmd(ospi_flash_t *self, uint32_t cmd, uint8_t cmd_dummy_cycles, size_t len, uint8_t *dest) {
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int ret = 0;
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if (self->set->inst_len == OSPI_INST_L_8bit) {
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ospi_setup_read_ext(&self->cfg, self->set->rxds, self->set->inst_len, OSPI_ADDR_L_0bit, OSPI_DATA_L_8bit, len, cmd_dummy_cycles);
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ret = ospi_recv_blocking_8bit_data(&self->cfg, cmd, dest);
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} else {
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uint16_t dest16 = 0;
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ospi_setup_read_ext(&self->cfg, self->set->rxds, self->set->inst_len, OSPI_ADDR_L_32bit, OSPI_DATA_L_16bit, len, cmd_dummy_cycles);
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ospi_push(&self->cfg, cmd);
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ret = ospi_recv_blocking_16bit_data(&self->cfg, 0 /* addr */, &dest16);
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*dest = dest16;
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}
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return ret;
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}
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static int ospi_flash_write_cmd_addr(ospi_flash_t *self, uint32_t cmd, uint32_t addr_len, uint32_t addr) {
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if (self->set->inst_len == OSPI_INST_L_8bit) {
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ospi_setup_write_ext(&self->cfg, false, self->set->inst_len, addr_len, OSPI_DATA_L_8bit);
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} else {
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ospi_setup_write_ext(&self->cfg, self->set->rxds, self->set->inst_len, addr_len, OSPI_DATA_L_16bit);
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}
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if (addr_len == OSPI_ADDR_L_0bit) {
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ospi_send_blocking(&self->cfg, cmd);
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} else {
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ospi_push(&self->cfg, cmd);
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ospi_send_blocking(&self->cfg, addr);
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}
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return 0;
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}
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static int ospi_flash_write_cmd(ospi_flash_t *self, uint32_t cmd) {
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return ospi_flash_write_cmd_addr(self, cmd, OSPI_ADDR_L_0bit, 0);
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}
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static uint32_t ospi_flash_read_id_spi(ospi_flash_t *self) {
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uint8_t buf[4] = {0x9f, 0, 0, 0};
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ospi_spi_transfer(&self->cfg, 4, buf, buf);
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return buf[1] | buf[2] << 8 | buf[3] << 16;
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}
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static int ospi_flash_wait_sr(ospi_flash_t *self, uint8_t mask, uint8_t val, uint32_t timeout) {
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do {
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uint8_t sr = 0;
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int ret = ospi_flash_read_cmd(self, self->set->read_sr, self->set->read_sr_dummy_cycles, 1, &sr);
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if (ret != 0) {
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return ret;
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}
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if ((sr & mask) == val) {
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return 0; // success
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}
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} while (timeout--);
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return -MP_ETIMEDOUT;
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}
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static int ospi_flash_wait_wel1(ospi_flash_t *self) {
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return ospi_flash_wait_sr(self, 2, 2, WAIT_SR_TIMEOUT);
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}
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static int ospi_flash_wait_wip0(ospi_flash_t *self) {
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return ospi_flash_wait_sr(self, 1, 0, WAIT_SR_TIMEOUT);
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}
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static uint32_t ospi_flash_read_id(ospi_flash_t *self) {
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uint8_t buf[4] = {0};
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if (self->set->inst_len == OSPI_INST_L_8bit) {
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ospi_setup_read_ext(&self->cfg, self->set->rxds, self->set->inst_len, OSPI_ADDR_L_0bit, OSPI_DATA_L_8bit, 3, self->set->read_id_dummy_cycles);
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ospi_recv_blocking_8bit_data(&self->cfg, self->set->read_id, buf);
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} else {
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ospi_setup_read_ext(&self->cfg, self->set->rxds, self->set->inst_len, OSPI_ADDR_L_32bit, OSPI_DATA_L_16bit, 4, self->set->read_id_dummy_cycles);
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ospi_push(&self->cfg, self->set->read_id);
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// Read 8-bit values because data is in SDR mode for read id.
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ospi_recv_blocking_8bit_data(&self->cfg, 0, buf);
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}
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return buf[0] | buf[1] << 8 | buf[2] << 16;
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}
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/******************************************************************************/
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// Functions specific to ISSI flash chips.
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int ospi_flash_issi_init(ospi_flash_t *self) {
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const uint8_t cmd_wrvol = 0x81;
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// Configure dummy cycles.
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ospi_flash_wren_spi(self);
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uint8_t buf0[5] = {cmd_wrvol, 0, 0, 1, self->set->read_dummy_cycles};
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ospi_spi_transfer(&self->cfg, sizeof(buf0), buf0, buf0);
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// Switch SPI flash to Octal DDR mode.
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const uint8_t issi_mode_octal_ddr_dqs = 0xe7;
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ospi_flash_wren_spi(self);
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uint8_t buf1[5] = {cmd_wrvol, 0, 0, 0, issi_mode_octal_ddr_dqs};
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ospi_spi_transfer(&self->cfg, sizeof(buf1), buf1, buf1);
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self->cfg.ddr_en = 1;
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return 0;
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}
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/******************************************************************************/
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// Functions specific to MX flash chips.
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int ospi_flash_mx_init(ospi_flash_t *self) {
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const uint8_t cmd_wrcr2 = 0x72;
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const uint8_t mx_mode_enable_sopi = 0x01;
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const uint8_t mx_mode_enable_dopi = 0x02;
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uint8_t mx_mode;
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if (self->set->octal_mode == OSPI_FLASH_OCTAL_MODE_DDD) {
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mx_mode = mx_mode_enable_dopi;
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} else {
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mx_mode = mx_mode_enable_sopi;
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}
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// Configure dummy cycles.
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uint8_t ddc_value = 0;
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const uint8_t ospi_flash_mx_ddc[][2] = {
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{20, 0}, {18, 1}, {16, 2}, {14, 3}, {12, 4}, {10, 5}, {8, 6}, {6, 7}
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};
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for (size_t i = 0; i < MP_ARRAY_SIZE(ospi_flash_mx_ddc); i++) {
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if (self->set->read_dummy_cycles == ospi_flash_mx_ddc[i][0]) {
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ddc_value = ospi_flash_mx_ddc[i][1];
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break;
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}
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}
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ospi_flash_wren_spi(self);
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uint8_t buf0[6] = {cmd_wrcr2, 0, 0, 3, 0, ddc_value};
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ospi_spi_transfer(&self->cfg, sizeof(buf0), buf0, buf0);
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// Switch SPI flash to Octal SDR or DDR mode.
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ospi_flash_wren_spi(self);
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uint8_t buf1[6] = {cmd_wrcr2, 0, 0, 0, 0, mx_mode};
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ospi_spi_transfer(&self->cfg, sizeof(buf1), buf1, buf1);
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if (self->set->octal_mode == OSPI_FLASH_OCTAL_MODE_DDD) {
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self->cfg.ddr_en = 1;
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} else {
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self->cfg.ddr_en = 0;
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}
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return 0;
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}
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static uint8_t ospi_flash_mx_read_cr_helper(ospi_flash_t *self, uint16_t command, uint32_t addr) {
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// TODO: currently only works in DDR mode
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uint16_t buf[1] = {0};
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ospi_setup_read_ext(&self->cfg, self->set->rxds, OSPI_INST_L_16bit, OSPI_ADDR_L_32bit, OSPI_DATA_L_16bit, 1, 4);
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ospi_push(&self->cfg, command);
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ospi_recv_blocking_16bit_data(&self->cfg, addr, buf);
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return buf[0] & 0xff;
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}
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uint8_t ospi_flash_mx_read_cr(ospi_flash_t *self) {
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return ospi_flash_mx_read_cr_helper(self, 0x15ea, 0);
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}
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uint8_t ospi_flash_mx_read_cr2(ospi_flash_t *self, uint32_t addr) {
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return ospi_flash_mx_read_cr_helper(self, 0x718e, addr);
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}
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static int ospi_flash_mx_write_cr_helper(ospi_flash_t *self, uint16_t command, uint32_t addr, uint8_t value) {
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// TODO: currently only works in DDR mode
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// Enable writes so that the register can be modified.
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ospi_flash_write_cmd(self, self->set->write_en);
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int ret = ospi_flash_wait_wel1(self);
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if (ret < 0) {
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return ret;
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}
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// Do the write.
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ospi_setup_write_ext(&self->cfg, self->set->rxds, OSPI_INST_L_16bit, OSPI_ADDR_L_32bit, OSPI_DATA_L_16bit);
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ospi_push(&self->cfg, command);
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ospi_push(&self->cfg, addr);
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ospi_push(&self->cfg, value << 8); // in DDR mode, MSByte contains the register value to write
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ospi_writel((&self->cfg), ser, self->cfg.ser);
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while ((ospi_readl((&self->cfg), sr) & (SR_TF_EMPTY | SR_BUSY)) != SR_TF_EMPTY) {
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}
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// Wait for the write to finish.
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return ospi_flash_wait_wip0(self);
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}
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int ospi_flash_mx_write_cr(ospi_flash_t *self, uint8_t value) {
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return ospi_flash_mx_write_cr_helper(self, 0x01fe, 1, value);
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}
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int ospi_flash_mx_write_cr2(ospi_flash_t *self, uint32_t addr, uint8_t value) {
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return ospi_flash_mx_write_cr_helper(self, 0x728d, addr, value);
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}
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/******************************************************************************/
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// SPI flash initialisation.
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int ospi_flash_init(void) {
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ospi_flash_t *self = &global_flash;
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const ospi_pin_settings_t *pin = &ospi_pin_settings;
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const ospi_flash_settings_t *set = NULL;
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self->pin = pin;
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unsigned int unit = pin->peripheral_number;
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mp_hal_pin_config(pin->pin_cs, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE,
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MP_HAL_PIN_SPEED_LOW, MP_HAL_PIN_DRIVE_12MA, MP_HAL_PIN_ALT(OSPI_SS0, unit), false);
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mp_hal_pin_config(pin->pin_clk_p, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE,
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MP_HAL_PIN_SPEED_HIGH, MP_HAL_PIN_DRIVE_12MA, MP_HAL_PIN_ALT(OSPI_SCLK, unit), false);
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if (pin->pin_clk_n != NULL) {
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mp_hal_pin_config(pin->pin_clk_n, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE,
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MP_HAL_PIN_SPEED_HIGH, MP_HAL_PIN_DRIVE_12MA, MP_HAL_PIN_ALT(OSPI_SCLKN, unit), false);
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}
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if (pin->pin_rwds != NULL) {
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mp_hal_pin_config(pin->pin_rwds, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE,
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MP_HAL_PIN_SPEED_HIGH, MP_HAL_PIN_DRIVE_12MA, MP_HAL_PIN_ALT(OSPI_RXDS, unit), true);
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if (pin->pin_rwds->port == PORT_10 && pin->pin_rwds->pin == PIN_7) {
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// Alif: P5_6 is needed to support proper alt function selection of P10_7.
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mp_hal_pin_config(pin_P5_6, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE,
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MP_HAL_PIN_SPEED_HIGH, MP_HAL_PIN_DRIVE_12MA, MP_HAL_PIN_ALT(OSPI_RXDS, unit), true);
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}
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}
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mp_hal_pin_config(pin->pin_d0, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE,
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MP_HAL_PIN_SPEED_HIGH, MP_HAL_PIN_DRIVE_12MA, MP_HAL_PIN_ALT(OSPI_D0, unit), true);
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mp_hal_pin_config(pin->pin_d1, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE,
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MP_HAL_PIN_SPEED_HIGH, MP_HAL_PIN_DRIVE_12MA, MP_HAL_PIN_ALT(OSPI_D1, unit), true);
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mp_hal_pin_config(pin->pin_d2, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_UP,
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MP_HAL_PIN_SPEED_HIGH, MP_HAL_PIN_DRIVE_12MA, MP_HAL_PIN_ALT(OSPI_D2, unit), true);
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mp_hal_pin_config(pin->pin_d3, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE,
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MP_HAL_PIN_SPEED_HIGH, MP_HAL_PIN_DRIVE_12MA, MP_HAL_PIN_ALT(OSPI_D3, unit), true);
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if (pin->pin_d4 != NULL) {
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mp_hal_pin_config(pin->pin_d4, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE,
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MP_HAL_PIN_SPEED_HIGH, MP_HAL_PIN_DRIVE_12MA, MP_HAL_PIN_ALT(OSPI_D4, unit), true);
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mp_hal_pin_config(pin->pin_d5, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE,
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MP_HAL_PIN_SPEED_HIGH, MP_HAL_PIN_DRIVE_12MA, MP_HAL_PIN_ALT(OSPI_D5, unit), true);
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mp_hal_pin_config(pin->pin_d6, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE,
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MP_HAL_PIN_SPEED_HIGH, MP_HAL_PIN_DRIVE_12MA, MP_HAL_PIN_ALT(OSPI_D6, unit), true);
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mp_hal_pin_config(pin->pin_d7, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE,
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MP_HAL_PIN_SPEED_HIGH, MP_HAL_PIN_DRIVE_12MA, MP_HAL_PIN_ALT(OSPI_D7, unit), true);
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}
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// Reset the SPI flash.
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mp_hal_pin_output(pin->pin_reset);
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mp_hal_pin_low(pin->pin_reset);
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mp_hal_delay_us(100);
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mp_hal_pin_high(pin->pin_reset);
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mp_hal_delay_us(1000);
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// Configure the OSPI peripheral.
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if (pin->peripheral_number == 0) {
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self->cfg.regs = (ssi_regs_t *)OSPI0_BASE;
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self->cfg.aes_regs = (aes_regs_t *)AES0_BASE;
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self->cfg.xip_base = (volatile void *)OSPI0_XIP_BASE;
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} else {
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self->cfg.regs = (ssi_regs_t *)OSPI1_BASE;
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self->cfg.aes_regs = (aes_regs_t *)AES1_BASE;
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self->cfg.xip_base = (volatile void *)OSPI1_XIP_BASE;
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}
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self->cfg.ser = 1; // enable slave select
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self->cfg.addrlen = 8; // 32-bit address length
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self->cfg.ddr_en = 0;
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self->cfg.wait_cycles = 0; // used only for ospi_xip_exit
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self->cfg.ospi_clock = 100000; // use 100KHz for detection.
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ospi_init(&self->cfg);
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// Read the device ID.
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uint32_t jedec_id = ospi_flash_read_id_spi(self);
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// Auto-detect the flash.
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for (size_t i = 0; i < ospi_flash_settings_len; i++) {
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set = &ospi_flash_settings[i];
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if (jedec_id == set->jedec_id) {
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self->set = set;
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break;
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}
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}
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if (self->set == NULL) {
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// Flash part is not supported.
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return -1;
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}
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// Switch to the higher frequency.
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self->cfg.ospi_clock = set->freq_hz;
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ospi_init(&self->cfg);
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// Switch to octal mode if needed.
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if (set->flash_init != NULL) {
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set->flash_init(self);
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// Check the device ID after switching mode.
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if (ospi_flash_read_id(self) != set->jedec_id) {
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return -1;
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}
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}
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// Enter XIP mode.
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ospi_flash_xip_enter(self);
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return 0;
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}
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uintptr_t ospi_flash_get_xip_base(void) {
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ospi_flash_t *self = &global_flash;
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return (uintptr_t)self->cfg.xip_base;
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}
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int ospi_flash_xip_enter(ospi_flash_t *self) {
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if (!self->xip_active) {
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uint32_t irq_state = disable_irq();
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self->xip_active = true;
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ospi_xip_enter_ext(&self->cfg, self->set->inst_len, self->set->xip_data_len,
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self->set->read_command, self->set->read_command, self->set->read_dummy_cycles);
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enable_irq(irq_state);
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}
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return 0;
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}
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int ospi_flash_xip_exit(ospi_flash_t *self) {
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if (self->xip_active) {
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uint32_t irq_state = disable_irq();
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ospi_xip_exit_ext(&self->cfg, self->set->inst_len, self->set->read_command, self->set->read_command);
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self->xip_active = false;
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enable_irq(irq_state);
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}
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return 0;
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}
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|
|
int ospi_flash_xip_restore(ospi_flash_t *self) {
|
|
if (self->xip_active) {
|
|
ospi_xip_restore_ext(&self->cfg, self->set->xip_data_len);
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
/******************************************************************************/
|
|
// Top-level read/erase/write functions.
|
|
|
|
int ospi_flash_erase_sector(uint32_t addr) {
|
|
ospi_flash_t *self = &global_flash;
|
|
|
|
ospi_flash_write_cmd(self, self->set->write_en);
|
|
int ret = ospi_flash_wait_wel1(self);
|
|
if (ret == 0) {
|
|
ospi_flash_write_cmd_addr(self, self->set->erase_command, OSPI_ADDR_L_32bit, addr);
|
|
ret = ospi_flash_wait_wip0(self);
|
|
}
|
|
|
|
ospi_flash_xip_restore(self);
|
|
|
|
return ret;
|
|
}
|
|
|
|
int ospi_flash_read(uint32_t addr, uint32_t len, uint8_t *dest) {
|
|
ospi_flash_t *self = &global_flash;
|
|
// Perform an XIP read (memcpy)
|
|
memcpy(dest, (void *)self->cfg.xip_base + addr, len);
|
|
return 0;
|
|
}
|
|
|
|
static int ospi_flash_write_page(uint32_t addr, uint32_t len, const uint8_t *src) {
|
|
ospi_flash_t *self = &global_flash;
|
|
|
|
ospi_flash_write_cmd(self, self->set->write_en);
|
|
int ret = ospi_flash_wait_wel1(self);
|
|
if (ret < 0) {
|
|
return ret;
|
|
}
|
|
|
|
ospi_setup_write_ext(&self->cfg, self->set->rxds, self->set->inst_len, OSPI_ADDR_L_32bit, OSPI_DATA_L_32bit);
|
|
ospi_push(&self->cfg, self->set->write_command);
|
|
ospi_push(&self->cfg, addr);
|
|
|
|
const uint32_t *src32 = (const uint32_t *)src;
|
|
if (self->set->bswap16) {
|
|
// MX flashes swap 16-bit words when read in 8D-8D-8D.
|
|
for (; len; len -= 4) {
|
|
ospi_push(&self->cfg, __ROR(*src32++, 16));
|
|
}
|
|
} else {
|
|
// For the rest of the flashes, we just correct the endianness.
|
|
for (; len; len -= 4) {
|
|
ospi_push(&self->cfg, __REV(*src32++));
|
|
}
|
|
}
|
|
|
|
ospi_writel((&self->cfg), ser, self->cfg.ser);
|
|
while ((ospi_readl((&self->cfg), sr) & (SR_TF_EMPTY | SR_BUSY)) != SR_TF_EMPTY) {
|
|
}
|
|
|
|
return ospi_flash_wait_wip0(self);
|
|
}
|
|
|
|
int ospi_flash_write(uint32_t addr, uint32_t len, const uint8_t *src) {
|
|
ospi_flash_t *self = &global_flash;
|
|
|
|
int ret = 0;
|
|
uint32_t offset = addr & (PAGE_SIZE - 1);
|
|
|
|
while (len) {
|
|
size_t rest = PAGE_SIZE - offset;
|
|
if (rest > len) {
|
|
rest = len;
|
|
}
|
|
ret = ospi_flash_write_page(addr, rest, src);
|
|
if (ret != 0) {
|
|
break;
|
|
}
|
|
len -= rest;
|
|
addr += rest;
|
|
src += rest;
|
|
offset = 0;
|
|
}
|
|
|
|
ospi_flash_xip_restore(self);
|
|
|
|
return ret;
|
|
}
|
|
|
|
#endif // MICROPY_HW_ENABLE_OSPI
|