Alessandro Gatti
424ae08680
py/asmrv32: Do not clobber index register on viper load/store.
...
This commit lets the native emitter preserve the value of the index
register when performing register-indexed loads or stores for halfword
or word values on RV32.
The original code was optimised too aggressively to reduce the generated
code's size, using compressed opcodes that alias the target register to
one of the operands. In register-indexed load/store operations, the
index register was assumed to be allocated somewhere safe, but it was
not always the case.
To solve this, now all halfword and word register-indexed operations
will use REG_TEMP2 to store the scaled index register. The size penalty
on generated code varies across operation sizes and enabled extensions:
- byte operations stay the same size with or without Zba
- halfword operations will be 2 bytes larger without Zba, and will stay
the same size with Zba
- word operations will be 4 bytes larger without Zba, and 2 bytes larger
with Zba
There is also a minor firmware footprint increase to hold the extra
logic needed for conditional register clobbering, but it shouldn't be
that large anyway.
Signed-off-by: Alessandro Gatti <a.gatti@frob.it >
2026-02-24 18:42:53 +11:00
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