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https://github.com/micropython/micropython.git
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40dbf77415
This commit adds support for Zba opcodes to the RV32 inline assembler. Three new opcodes were added, SH1ADD, SH2ADD, and SH3ADD, which performs a scaled addition (by 1, 2, or 3 bits respectively). At the moment only qemu's VIRT_RV32 and rp2's RPI_PICO2/RPI_PICO2_W ports support these opcodes (the latter only when using the RISCV variant). Signed-off-by: Alessandro Gatti <a.gatti@frob.it>
19 lines
312 B
Python
19 lines
312 B
Python
@micropython.asm_rv32
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def test_sh1add(a0, a1):
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sh1add(a0, a0, a1)
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@micropython.asm_rv32
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def test_sh2add(a0, a1):
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sh2add(a0, a0, a1)
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@micropython.asm_rv32
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def test_sh3add(a0, a1):
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sh3add(a0, a0, a1)
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print(hex(test_sh1add(10, 20)))
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print(hex(test_sh2add(10, 20)))
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print(hex(test_sh3add(10, 20)))
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