Files
micropython/ports
Andrew Leech a23f69ea68 stm32/machine_adc: Fix ADC V2 CR register writes and timeouts.
Replace all |= on ADC CR with mask-and-set using ADC_CR_BITS_PROPERTY_RS
from the LL HAL. On ADC V2 the CR command bits are write-1-to-set, so |=
can propagate stale bits (e.g. ADSTP left by HAL_ADC_Stop), violating the
RM requirement that ADSTART and ADSTP must not be asserted simultaneously.

Add recovery logic in adc_config_channel for stuck ADSTART: stop the
conversion, disable, and re-enable the ADC before reconfiguring SQR1.

Replace unbounded while loops in ADC V2 paths with ADC_WAIT, a busy-wait
macro using mp_hal_ticks_ms with a 250ms timeout.

Signed-off-by: Andrew Leech <andrew.leech@planetinnovation.com.au>
2026-04-30 23:03:29 +10:00
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