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This commit adds support for Zba opcodes to the RV32 inline assembler. Three new opcodes were added, SH1ADD, SH2ADD, and SH3ADD, which performs a scaled addition (by 1, 2, or 3 bits respectively). At the moment only qemu's VIRT_RV32 and rp2's RPI_PICO2/RPI_PICO2_W ports support these opcodes (the latter only when using the RISCV variant). Signed-off-by: Alessandro Gatti <a.gatti@frob.it>
This directory doesn't contain real tests, but code snippets to detect various interpreter features, which can't be/inconvenient to detect by other means. Scripts here are executed by run-tests.py at the beginning of testsuite to decide what other test groups to run/exclude.