Lerking/nanoBench
1
0
Fork 0
mirror of https://github.com/andreas-abel/nanoBench.git synced 2026-01-06 20:30:13 +01:00
Code Issues Packages Projects Releases Wiki Activity

support for Tremont

Browse Source
This commit is contained in:
Andreas Abel
2022-01-18 19:01:33 +01:00
parent 5bffd03b71
commit 15b1ccb275
5 changed files with 385 additions and 5 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
tools/cpuBench/cpuBench.py
View File

@@ -212,6 +212,7 @@ def runExperiment(instrNode, instrCode, init=None, unrollCount=500, loopCount=0,
elif arch in ['SNB', 'SLM', 'AMT', 'ADL-E']: evt = 'UOPS_RETIRED.ALL'
elif arch in ['HSW']: evt = 'UOPS_EXECUTED.CORE'
elif arch in ['IVB', 'BDW', 'SKL', 'SKX', 'KBL', 'CFL', 'CNL', 'ICL', 'CLX', 'TGL', 'RKL', 'ADL-P']: evt = 'UOPS_EXECUTED.THREAD'
elif arch in ['TRM']: evt = 'TOPDOWN_RETIRING.ALL'
localHtmlReports.append('<li>' + evt + ': ' + str(value) + '</li>\n')
localHtmlReports.append('</ul>\n</li>')
@@ -276,6 +277,7 @@ def getEventConfig(event):
if arch in ['NHM', 'WSM', 'SNB' ]: return 'C2.01' # UOPS_RETIRED.ANY
if arch in ['SNB']: return 'C2.01' # UOPS_RETIRED.ALL
if arch in ['GLM', 'GLP', 'ADL-E']: return 'C2.00' # UOPS_RETIRED.ALL
if arch in ['TRM']: return 'C2.00' # TOPDOWN_RETIRING.ALL
if arch in ['BNL', 'SLM', 'AMT']: return 'C2.10' # UOPS_RETIRED.ANY
if arch in ['HSW']: return 'B1.02' # UOPS_EXECUTED.CORE; note: may undercount due to erratum HSD30
if arch in ['IVB', 'BDW', 'SKL', 'SKX', 'KBL', 'CFL', 'CNL', 'ICL', 'CLX', 'TGL', 'RKL', 'ADL-P']: return 'B1.01' # UOPS_EXECUTED.THREAD
@@ -290,7 +292,7 @@ def getEventConfig(event):
if arch in ['NHM', 'WSM']: return 'D1.02'
if arch in ['SNB', 'IVB', 'HSW', 'BDW', 'SKL', 'SKX', 'KBL', 'CFL', 'CNL', 'ICL', 'CLX', 'TGL', 'RKL']: return '79.30'
if arch in ['ADL-P']: return '79.20'
if arch in ['SLM', 'AMT', 'GLM', 'GLP', 'ADL-E']: return 'C2.01'
if arch in ['SLM', 'AMT', 'GLM', 'GLP', 'TRM', 'ADL-E']: return 'C2.01'
if arch in ['BNL']: return 'A9.01' # undocumented, but seems to work
if event == 'UOPS_PORT_0':
if arch in ['CON', 'WOL']: return 'A1.01.CTR=0'
@@ -1356,7 +1358,7 @@ def getBasicLatencies(instrNodeList):
if testSetCycles == 2:
basicLatency['TEST'] = 1
elif arch in ['BNL', 'SLM', 'AMT', 'GLM', 'GLP']:
elif arch in ['BNL', 'SLM', 'AMT', 'GLM', 'GLP', 'TRM']:
# according to the Optimization Manual (June 2021)
basicLatency['TEST'] = 1
else:
@@ -2909,7 +2911,9 @@ def filterInstructions(XMLRoot):
if category == 'GFNI':
if not cpuid.get_bit(ecx7, 8):
instrSet.discard(XMLInstr)
elif 'AVX512' in isaSet and not cpuid.get_bit(ebx7, 31):
elif ('AVX' in isaSet) and (not cpuid.get_bit(ecx1, 28)):
instrSet.discard(XMLInstr)
elif ('AVX512' in isaSet) and (not cpuid.get_bit(ebx7, 31)):
instrSet.discard(XMLInstr)
if 'VAES' in isaSet:
if not cpuid.get_bit(ecx7, 9):