diff --git a/configs/cfg_Core_all.txt b/configs/cfg_Core_all.txt
new file mode 100644
index 0000000..c0f4ded
--- /dev/null
+++ b/configs/cfg_Core_all.txt
@@ -0,0 +1,386 @@
+# Performance monitoring events for processors based on the Core and the Enhanced Core microarchitectures.
+# See Table 19-26 of Intel's "System Programming Guide" (Jan. 2019)
+
+03.02 LOAD_BLOCK.STA
+03.04 LOAD_BLOCK.STD
+03.08 LOAD_BLOCK.OVERLAP_STORE
+03.10 LOAD_BLOCK.UNTIL_RETIRE
+03.20 LOAD_BLOCK.L1D
+04.01 SB_DRAIN_CYCLES
+04.02 STORE_BLOCK.ORDER
+04.08 STORE_BLOCK.SNOOP
+06.00 SEGMENT_REG_LOADS
+07.00 SSE_PRE_EXEC.NTA
+07.01 SSE_PRE_EXEC.L1
+07.02 SSE_PRE_EXEC.L2
+07.03 SSE_PRE_EXEC.STORES
+08.01 DTLB_MISSES.ANY
+08.02 DTLB_MISSES.MISS_LD
+08.04 DTLB_MISSES.L0_MISS_LD
+08.08 DTLB_MISSES.MISS_ST
+09.01 MEMORY_DISAMBIGUATION.RESET
+09.02 MEMORY_DISAMBIGUATION.SUCCESS
+0C.01 PAGE_WALKS.COUNT
+0C.02 PAGE_WALKS.CYCLES
+10.00.CTR=0 FP_COMP_OPS_EXE
+11.00.CTR=1 FP_ASSIST
+12.00.CTR=1 MUL
+13.00.CTR=1 DIV
+14.00.CTR=0 CYCLES_DIV_BUSY
+18.00.CTR=0 IDLE_DURING_DIV
+19.00.CTR=1 DELAYED_BYPASS.FP
+19.01.CTR=1 DELAYED_BYPASS.SIMD
+19.02.CTR=1 DELAYED_BYPASS.LOAD
+21.40 L2_ADS.THIS_CORE
+21.C0 L2_ADS.ALL_CORES
+23.40 L2_DBUS_BUSY_RD.THIS_CORE
+23.C0 L2_DBUS_BUSY_RD.ALL_CORES
+24.70 L2_LINES_IN.THIS_CORE.ALL_INCL
+24.50 L2_LINES_IN.THIS_CORE.HW_PF
+24.40 L2_LINES_IN.THIS_CORE.EXCL_HW_PF
+24.F0 L2_LINES_IN.ALL_CORES.ALL_INCL
+24.D0 L2_LINES_IN.ALL_CORES.HW_PF
+24.C0 L2_LINES_IN.ALL_CORES.EXCL_HW_PF
+25.40 L2_M_LINES_IN.THIS_CORE
+25.C0 L2_M_LINES_IN.ALL_CORES
+26.70 L2_LINES_OUT.THIS_CORE.ALL_INCL
+26.50 L2_LINES_OUT.THIS_CORE.HW_PF
+26.40 L2_LINES_OUT.THIS_CORE.EXCL_HW_PF
+26.F0 L2_LINES_OUT.ALL_CORES.ALL_INCL
+26.D0 L2_LINES_OUT.ALL_CORES.HW_PF
+26.C0 L2_LINES_OUT.ALL_CORES.EXCL_HW_PF
+27.70 L2_M_LINES_OUT.THIS_CORE.ALL_INCL
+27.50 L2_M_LINES_OUT.THIS_CORE.HW_PF
+27.40 L2_M_LINES_OUT.THIS_CORE.EXCL_HW_PF
+27.F0 L2_M_LINES_OUT.ALL_CORES.ALL_INCL
+27.D0 L2_M_LINES_OUT.ALL_CORES.HW_PF
+27.C0 L2_M_LINES_OUT.ALL_CORES.EXCL_HW_PF
+28.48 L2_IFETCH.THIS_CORE.M
+28.44 L2_IFETCH.THIS_CORE.E
+28.42 L2_IFETCH.THIS_CORE.S
+28.41 L2_IFETCH.THIS_CORE.I
+28.C8 L2_IFETCH.ALL_CORES.M
+28.C4 L2_IFETCH.ALL_CORES.E
+28.C2 L2_IFETCH.ALL_CORES.S
+28.C1 L2_IFETCH.ALL_CORES.I
+29.78 L2_LD.THIS_CORE.ALL_INCL.M
+29.74 L2_LD.THIS_CORE.ALL_INCL.E
+29.72 L2_LD.THIS_CORE.ALL_INCL.S
+29.71 L2_LD.THIS_CORE.ALL_INCL.I
+29.58 L2_LD.THIS_CORE.HW_PF.M
+29.54 L2_LD.THIS_CORE.HW_PF.E
+29.52 L2_LD.THIS_CORE.HW_PF.S
+29.51 L2_LD.THIS_CORE.HW_PF.I
+29.48 L2_LD.THIS_CORE.EXCL_HW_PF.M
+29.44 L2_LD.THIS_CORE.EXCL_HW_PF.E
+29.42 L2_LD.THIS_CORE.EXCL_HW_PF.S
+29.41 L2_LD.THIS_CORE.EXCL_HW_PF.I
+29.F8 L2_LD.ALL_CORES.ALL_INCL.M
+29.F4 L2_LD.ALL_CORES.ALL_INCL.E
+29.F2 L2_LD.ALL_CORES.ALL_INCL.S
+29.F1 L2_LD.ALL_CORES.ALL_INCL.I
+29.D8 L2_LD.ALL_CORES.HW_PF.M
+29.D4 L2_LD.ALL_CORES.HW_PF.E
+29.D2 L2_LD.ALL_CORES.HW_PF.S
+29.D1 L2_LD.ALL_CORES.HW_PF.I
+29.C8 L2_LD.ALL_CORES.EXCL_HW_PF.M
+29.C4 L2_LD.ALL_CORES.EXCL_HW_PF.E
+29.C2 L2_LD.ALL_CORES.EXCL_HW_PF.S
+29.C1 L2_LD.ALL_CORES.EXCL_HW_PF.I
+2A.48 L2_ST.THIS_CORE.M
+2A.44 L2_ST.THIS_CORE.E
+2A.42 L2_ST.THIS_CORE.S
+2A.41 L2_ST.THIS_CORE.I
+2A.C8 L2_ST.ALL_CORES.M
+2A.C4 L2_ST.ALL_CORES.E
+2A.C2 L2_ST.ALL_CORES.S
+2A.C1 L2_ST.ALL_CORES.I
+2B.48 L2_LOCK.THIS_CORE.M
+2B.44 L2_LOCK.THIS_CORE.E
+2B.42 L2_LOCK.THIS_CORE.S
+2B.41 L2_LOCK.THIS_CORE.I
+2B.C8 L2_LOCK.ALL_CORES.M
+2B.C4 L2_LOCK.ALL_CORES.E
+2B.C2 L2_LOCK.ALL_CORES.S
+2B.C1 L2_LOCK.ALL_CORES.I
+2E.78 L2_RQSTS.THIS_CORE.ALL_INCL.M
+2E.74 L2_RQSTS.THIS_CORE.ALL_INCL.E
+2E.72 L2_RQSTS.THIS_CORE.ALL_INCL.S
+2E.71 L2_RQSTS.THIS_CORE.ALL_INCL.I
+2E.58 L2_RQSTS.THIS_CORE.HW_PF.M
+2E.54 L2_RQSTS.THIS_CORE.HW_PF.E
+2E.52 L2_RQSTS.THIS_CORE.HW_PF.S
+2E.51 L2_RQSTS.THIS_CORE.HW_PF.I
+2E.48 L2_RQSTS.THIS_CORE.EXCL_HW_PF.M
+2E.44 L2_RQSTS.THIS_CORE.EXCL_HW_PF.E
+2E.42 L2_RQSTS.THIS_CORE.EXCL_HW_PF.S
+2E.41 L2_RQSTS.THIS_CORE.EXCL_HW_PF.I
+2E.F8 L2_RQSTS.ALL_CORES.ALL_INCL.M
+2E.F4 L2_RQSTS.ALL_CORES.ALL_INCL.E
+2E.F2 L2_RQSTS.ALL_CORES.ALL_INCL.S
+2E.F1 L2_RQSTS.ALL_CORES.ALL_INCL.I
+2E.D8 L2_RQSTS.ALL_CORES.HW_PF.M
+2E.D4 L2_RQSTS.ALL_CORES.HW_PF.E
+2E.D2 L2_RQSTS.ALL_CORES.HW_PF.S
+2E.D1 L2_RQSTS.ALL_CORES.HW_PF.I
+2E.C8 L2_RQSTS.ALL_CORES.EXCL_HW_PF.M
+2E.C4 L2_RQSTS.ALL_CORES.EXCL_HW_PF.E
+2E.C2 L2_RQSTS.ALL_CORES.EXCL_HW_PF.S
+2E.C1 L2_RQSTS.ALL_CORES.EXCL_HW_PF.I
+2E.41 L2_RQSTS.SELF.DEMAND.I_STATE
+2E.4F L2_RQSTS.SELF.DEMAND.MESI
+30.78 L2_REJECT_BUSQ.THIS_CORE.ALL_INCL.M
+30.74 L2_REJECT_BUSQ.THIS_CORE.ALL_INCL.E
+30.72 L2_REJECT_BUSQ.THIS_CORE.ALL_INCL.S
+30.71 L2_REJECT_BUSQ.THIS_CORE.ALL_INCL.I
+30.58 L2_REJECT_BUSQ.THIS_CORE.HW_PF.M
+30.54 L2_REJECT_BUSQ.THIS_CORE.HW_PF.E
+30.52 L2_REJECT_BUSQ.THIS_CORE.HW_PF.S
+30.51 L2_REJECT_BUSQ.THIS_CORE.HW_PF.I
+30.48 L2_REJECT_BUSQ.THIS_CORE.EXCL_HW_PF.M
+30.44 L2_REJECT_BUSQ.THIS_CORE.EXCL_HW_PF.E
+30.42 L2_REJECT_BUSQ.THIS_CORE.EXCL_HW_PF.S
+30.41 L2_REJECT_BUSQ.THIS_CORE.EXCL_HW_PF.I
+30.F8 L2_REJECT_BUSQ.ALL_CORES.ALL_INCL.M
+30.F4 L2_REJECT_BUSQ.ALL_CORES.ALL_INCL.E
+30.F2 L2_REJECT_BUSQ.ALL_CORES.ALL_INCL.S
+30.F1 L2_REJECT_BUSQ.ALL_CORES.ALL_INCL.I
+30.D8 L2_REJECT_BUSQ.ALL_CORES.HW_PF.M
+30.D4 L2_REJECT_BUSQ.ALL_CORES.HW_PF.E
+30.D2 L2_REJECT_BUSQ.ALL_CORES.HW_PF.S
+30.D1 L2_REJECT_BUSQ.ALL_CORES.HW_PF.I
+30.C8 L2_REJECT_BUSQ.ALL_CORES.EXCL_HW_PF.M
+30.C4 L2_REJECT_BUSQ.ALL_CORES.EXCL_HW_PF.E
+30.C2 L2_REJECT_BUSQ.ALL_CORES.EXCL_HW_PF.S
+30.C1 L2_REJECT_BUSQ.ALL_CORES.EXCL_HW_PF.I
+32.40 L2_NO_REQ.THIS_CORE
+32.C0 L2_NO_REQ.ALL_CORES
+3A.00 EIST_TRANS
+3B.C0 THERMAL_TRIP
+3C.00 CPU_CLK_UNHALTED.
+3C.01 CPU_CLK_UNHALTED.BUS
+3C.02 CPU_CLK_UNHALTED.NO
+40.08 L1D_CACHE_LD.M
+40.04 L1D_CACHE_LD.E
+40.02 L1D_CACHE_LD.S
+40.01 L1D_CACHE_LD.I
+41.08 L1D_CACHE_ST.M
+41.04 L1D_CACHE_ST.E
+41.02 L1D_CACHE_ST.S
+41.01 L1D_CACHE_ST.I
+42.08 L1D_CACHE_LOCK.M
+42.04 L1D_CACHE_LOCK.E
+42.02 L1D_CACHE_LOCK.S
+42.01 L1D_CACHE_LOCK.I
+42.10 L1D_CACHE_LOCK_DURATION
+43.01 L1D_ALL_REF
+43.02 L1D_ALL_CACHE_REF
+45.0F L1D_REPL
+46.00 L1D_M_REPL
+47.00 L1D_M_EVICT
+48.00 L1D_PEND_MISS
+49.01 L1D_SPLIT.LOADS
+49.02 L1D_SPLIT.STORES
+4B.00 SSE_PRE_MISS.NTA
+4B.01 SSE_PRE_MISS.L1
+4B.02 SSE_PRE_MISS.L2
+4C.00 LOAD_HIT_PRE
+4E.10 L1D_PREFETCH.REQUESTS
+60.40 BUS_REQUEST_OUTSTANDING.THIS_CORE.THIS_AGENT
+60.60 BUS_REQUEST_OUTSTANDING.THIS_CORE.ALL_AGENTS
+60.C0 BUS_REQUEST_OUTSTANDING.ALL_CORES.THIS_AGENT
+60.E0 BUS_REQUEST_OUTSTANDING.ALL_CORES.ALL_AGENTS
+61.00 BUS_BNR_DRV.THIS_AGENT
+61.20 BUS_BNR_DRV.ALL_AGENTS
+62.00 BUS_DRDY_CLOCKS.THIS_AGENT
+62.20 BUS_DRDY_CLOCKS.ALL_AGENTS
+63.40 BUS_LOCK_CLOCKS.THIS_CORE.THIS_AGENT
+63.60 BUS_LOCK_CLOCKS.THIS_CORE.ALL_AGENTS
+63.C0 BUS_LOCK_CLOCKS.ALL_CORES.THIS_AGENT
+63.E0 BUS_LOCK_CLOCKS.ALL_CORES.ALL_AGENTS
+64.40 BUS_DATA_RCV.THIS_CORE
+64.C0 BUS_DATA_RCV.ALL_CORES
+65.40 BUS_TRANS_BRD.THIS_CORE.THIS_AGENT
+65.60 BUS_TRANS_BRD.THIS_CORE.ALL_AGENTS
+65.C0 BUS_TRANS_BRD.ALL_CORES.THIS_AGENT
+65.E0 BUS_TRANS_BRD.ALL_CORES.ALL_AGENTS
+66.40 BUS_TRANS_RFO.THIS_CORE.THIS_AGENT
+66.60 BUS_TRANS_RFO.THIS_CORE.ALL_AGENTS
+66.C0 BUS_TRANS_RFO.ALL_CORES.THIS_AGENT
+66.E0 BUS_TRANS_RFO.ALL_CORES.ALL_AGENTS
+67.40 BUS_TRANS_WB.THIS_CORE.THIS_AGENT
+67.60 BUS_TRANS_WB.THIS_CORE.ALL_AGENTS
+67.C0 BUS_TRANS_WB.ALL_CORES.THIS_AGENT
+67.E0 BUS_TRANS_WB.ALL_CORES.ALL_AGENTS
+68.40 BUS_TRANS_IFETCH.THIS_CORE.THIS_AGENT
+68.60 BUS_TRANS_IFETCH.THIS_CORE.ALL_AGENTS
+68.C0 BUS_TRANS_IFETCH.ALL_CORES.THIS_AGENT
+68.E0 BUS_TRANS_IFETCH.ALL_CORES.ALL_AGENTS
+69.40 BUS_TRANS_INVAL.THIS_CORE.THIS_AGENT
+69.60 BUS_TRANS_INVAL.THIS_CORE.ALL_AGENTS
+69.C0 BUS_TRANS_INVAL.ALL_CORES.THIS_AGENT
+69.E0 BUS_TRANS_INVAL.ALL_CORES.ALL_AGENTS
+6A.40 BUS_TRANS_PWR.THIS_CORE.THIS_AGENT
+6A.60 BUS_TRANS_PWR.THIS_CORE.ALL_AGENTS
+6A.C0 BUS_TRANS_PWR.ALL_CORES.THIS_AGENT
+6A.E0 BUS_TRANS_PWR.ALL_CORES.ALL_AGENTS
+6B.40 BUS_TRANS_P.THIS_CORE.THIS_AGENT
+6B.60 BUS_TRANS_P.THIS_CORE.ALL_AGENTS
+6B.C0 BUS_TRANS_P.ALL_CORES.THIS_AGENT
+6B.E0 BUS_TRANS_P.ALL_CORES.ALL_AGENTS
+6C.40 BUS_TRANS_IO.THIS_CORE.THIS_AGENT
+6C.60 BUS_TRANS_IO.THIS_CORE.ALL_AGENTS
+6C.C0 BUS_TRANS_IO.ALL_CORES.THIS_AGENT
+6C.E0 BUS_TRANS_IO.ALL_CORES.ALL_AGENTS
+6D.40 BUS_TRANS_DEF.THIS_CORE.THIS_AGENT
+6D.60 BUS_TRANS_DEF.THIS_CORE.ALL_AGENTS
+6D.C0 BUS_TRANS_DEF.ALL_CORES.THIS_AGENT
+6D.E0 BUS_TRANS_DEF.ALL_CORES.ALL_AGENTS
+6E.40 BUS_TRANS_BURST.THIS_CORE.THIS_AGENT
+6E.60 BUS_TRANS_BURST.THIS_CORE.ALL_AGENTS
+6E.C0 BUS_TRANS_BURST.ALL_CORES.THIS_AGENT
+6E.E0 BUS_TRANS_BURST.ALL_CORES.ALL_AGENTS
+6F.40 BUS_TRANS_MEM.THIS_CORE.THIS_AGENT
+6F.60 BUS_TRANS_MEM.THIS_CORE.ALL_AGENTS
+6F.C0 BUS_TRANS_MEM.ALL_CORES.THIS_AGENT
+6F.E0 BUS_TRANS_MEM.ALL_CORES.ALL_AGENTS
+70.40 BUS_TRANS_ANY.THIS_CORE.THIS_AGENT
+70.60 BUS_TRANS_ANY.THIS_CORE.ALL_AGENTS
+70.C0 BUS_TRANS_ANY.ALL_CORES.THIS_AGENT
+70.E0 BUS_TRANS_ANY.ALL_CORES.ALL_AGENTS
+77.08 EXT_SNOOP.THIS_AGENT.HITM
+77.02 EXT_SNOOP.THIS_AGENT.HIT
+77.01 EXT_SNOOP.THIS_AGENT.CLEAN
+77.28 EXT_SNOOP.ALL_AGENTS.HITM
+77.22 EXT_SNOOP.ALL_AGENTS.HIT
+77.21 EXT_SNOOP.ALL_AGENTS.CLEAN
+78.42 CMP_SNOOP.THIS_CORE.CMP2I
+78.41 CMP_SNOOP.THIS_CORE.CMP2S
+78.C2 CMP_SNOOP.ALL_CORES.CMP2I
+78.C1 CMP_SNOOP.ALL_CORES.CMP2S
+7A.00 BUS_HIT_DRV.THIS_AGENT
+7A.20 BUS_HIT_DRV.ALL_AGENTS
+7B.00 BUS_HITM_DRV.THIS_AGENT
+7B.20 BUS_HITM_DRV.ALL_AGENTS
+7D.40 BUSQ_EMPTY.THIS_CORE
+7D.C0 BUSQ_EMPTY.ALL_CORES
+7E.40 SNOOP_STALL_DRV.THIS_CORE.THIS_AGENT
+7E.60 SNOOP_STALL_DRV.THIS_CORE.ALL_AGENTS
+7E.C0 SNOOP_STALL_DRV.ALL_CORES.THIS_AGENT
+7E.E0 SNOOP_STALL_DRV.ALL_CORES.ALL_AGENTS
+7F.40 BUS_IO_WAIT.THIS_CORE
+7F.C0 BUS_IO_WAIT.ALL_CORES
+80.00 L1I_READS
+81.00 L1I_MISSES
+82.02 ITLB.SMALL_MISS
+82.10 ITLB.LARGE_MISS
+82.40 ITLB.FLUSH
+82.12 ITLB.MISSES
+83.02 INST_QUEUE.FULL
+86.00 CYCLES_L1I_MEM_STALLED
+87.00 ILD_STALL
+88.00 BR_INST_EXEC
+89.00 BR_MISSP_EXEC
+8A.00 BR_BAC_MISSP_EXEC
+8B.00 BR_CND_EXEC
+8C.00 BR_CND_MISSP_EXEC
+8D.00 BR_IND_EXEC
+8E.00 BR_IND_MISSP_EXEC
+8F.00 BR_RET_EXEC
+90.00 BR_RET_MISSP_EXEC
+91.00 BR_RET_BAC_MISSP_EXEC
+92.00 BR_CALL_EXEC
+93.00 BR_CALL_MISSP_EXEC
+94.00 BR_IND_CALL_EXEC
+97.00 BR_TKN_BUBBLE_1
+98.00 BR_TKN_BUBBLE_2
+A0.00 RS_UOPS_DISPATCHED
+A1.01.CTR=0 RS_UOPS_DISPATCHED.PORT0
+A1.02.CTR=0 RS_UOPS_DISPATCHED.PORT1
+A1.04.CTR=0 RS_UOPS_DISPATCHED.PORT2
+A1.08.CTR=0 RS_UOPS_DISPATCHED.PORT3
+A1.10.CTR=0 RS_UOPS_DISPATCHED.PORT4
+A1.20.CTR=0 RS_UOPS_DISPATCHED.PORT5
+AA.01 MACRO_INSTS.DECODED
+AA.08 MACRO_INSTS.CISC_DECODED
+AB.01 ESP.SYNCH
+AB.02 ESP.ADDITIONS
+B0.00 SIMD_UOPS_EXEC
+B1.00 SIMD_SAT_UOP_EXEC
+B3.01 SIMD_UOP_TYPE_EXEC.MUL
+B3.02 SIMD_UOP_TYPE_EXEC.SHIFT
+B3.04 SIMD_UOP_TYPE_EXEC.PACK
+B3.08 SIMD_UOP_TYPE_EXEC.UNPACK
+B3.10 SIMD_UOP_TYPE_EXEC.LOGICAL
+B3.20 SIMD_UOP_TYPE_EXEC.ARITHMETIC
+C0.00 INST_RETIRED.ANY_P
+C0.01 INST_RETIRED.LOADS
+C0.02 INST_RETIRED.STORES
+C0.04 INST_RETIRED.OTHER
+C1.01 X87_OPS_RETIRED.FXCH
+C1.FE X87_OPS_RETIRED.ANY
+C2.01 UOPS_RETIRED.LD_IND_BR
+C2.02 UOPS_RETIRED.STD_STA
+C2.04 UOPS_RETIRED.MACRO_FUSION
+C2.07 UOPS_RETIRED.FUSED
+C2.08 UOPS_RETIRED.NON_FUSED
+C2.0F UOPS_RETIRED.ANY
+C3.01 MACHINE_NUKES.SMC
+C3.04 MACHINE_NUKES.MEM_ORDER
+C4.00 BR_INST_RETIRED.ANY
+C4.01 BR_INST_RETIRED.PRED_NOT_
+C4.02 BR_INST_RETIRED.MISPRED_NOT_
+C4.04 BR_INST_RETIRED.PRED_TAKEN
+C4.08 BR_INST_RETIRED.MISPRED_TAKEN
+C4.0C BR_INST_RETIRED.TAKEN
+C5.00 BR_INST_RETIRED.MISPRED
+C6.01 CYCLES_INT_MASKED
+C6.02 CYCLES_INT_PENDING_AND_MASKED
+C7.01 SIMD_INST_RETIRED.PACKED_SINGLE
+C7.02 SIMD_INST_RETIRED.SCALAR_SINGLE
+C7.04 SIMD_INST_RETIRED.PACKED_DOUBLE
+C7.08 SIMD_INST_RETIRED.SCALAR_DOUBLE
+C7.10 SIMD_INST_RETIRED.VECTOR
+C7.1F SIMD_INST_RETIRED.ANY
+C8.00 HW_INT_RCV
+C9.00 ITLB_MISS_RETIRED
+CA.01 SIMD_COMP_INST_RETIRED.PACKED_SINGLE
+CA.02 SIMD_COMP_INST_RETIRED.SCALAR_SINGLE
+CA.04 SIMD_COMP_INST_RETIRED.PACKED_DOUBLE
+CA.08 SIMD_COMP_INST_RETIRED.SCALAR_DOUBLE
+CB.01.CTR=0 MEM_LOAD_RETIRED.L1D_MISS
+CB.02.CTR=0 MEM_LOAD_RETIRED.L1D_LINE_MISS
+CB.04.CTR=0 MEM_LOAD_RETIRED.L2_MISS
+CB.08.CTR=0 MEM_LOAD_RETIRED.L2_LINE_MISS
+CB.10.CTR=0 MEM_LOAD_RETIRED.DTLB_MISS
+CC.01 FP_MMX_TRANS_TO_MMX
+CC.02 FP_MMX_TRANS_TO_FP
+CD.00 SIMD_ASSIST
+CE.00 SIMD_INSTR_RETIRED
+CF.00 SIMD_SAT_INSTR_RETIRED
+D2.01 RAT_STALLS.ROB_READ_PORT
+D2.02 RAT_STALLS.PARTIAL_CYCLES
+D2.04 RAT_STALLS.FLAGS
+D2.08 RAT_STALLS.FPSW
+D2.0F RAT_STALLS.ANY
+D4.01 SEG_RENAME_STALLS.ES
+D4.02 SEG_RENAME_STALLS.DS
+D4.04 SEG_RENAME_STALLS.FS
+D4.08 SEG_RENAME_STALLS.GS
+D4.0F SEG_RENAME_STALLS.ANY
+D5.01 SEG_REG_RENAMES.ES
+D5.02 SEG_REG_RENAMES.DS
+D5.04 SEG_REG_RENAMES.FS
+D5.08 SEG_REG_RENAMES.GS
+D5.0F SEG_REG_RENAMES.ANY
+DC.01 RESOURCE_STALLS.ROB_FULL
+DC.02 RESOURCE_STALLS.RS_FULL
+DC.04 RESOURCE_STALLS.LD_ST
+DC.08 RESOURCE_STALLS.FPCW
+DC.10 RESOURCE_STALLS.BR_MISS_CLEAR
+DC.1F RESOURCE_STALLS.ANY
+E0.00 BR_INST_DECODED
+E4.00 BOGUS_BR
+E6.00 BACLEARS
+F0.00 PREF_RQSTS_UP
+F8.00 PREF_RQSTS_DN
\ No newline at end of file
diff --git a/configs/cfg_Core_common.txt b/configs/cfg_Core_common.txt
new file mode 100644
index 0000000..e237041
--- /dev/null
+++ b/configs/cfg_Core_common.txt
@@ -0,0 +1,32 @@
+# Performance monitoring events for processors based on the Core and the Enhanced Core microarchitectures.
+# See Table 19-26 of Intel's "System Programming Guide" (Jan. 2019)
+
+C2.07 UOPS_RETIRED.FUSED
+C2.0F UOPS_RETIRED.ANY
+A0.00 RS_UOPS_DISPATCHED
+A1.01.CTR=0 RS_UOPS_DISPATCHED.PORT0
+A1.02.CTR=0 RS_UOPS_DISPATCHED.PORT1
+A1.04.CTR=0 RS_UOPS_DISPATCHED.PORT2
+A1.08.CTR=0 RS_UOPS_DISPATCHED.PORT3
+A1.10.CTR=0 RS_UOPS_DISPATCHED.PORT4
+A1.20.CTR=0 RS_UOPS_DISPATCHED.PORT5
+88.00 BR_INST_EXEC
+89.00 BR_MISSP_EXEC
+43.02 L1D_ALL_CACHE_REF
+45.0F L1D_REPL
+CB.01.CTR=0 MEM_LOAD_RETIRED.L1D_MISS
+CB.02.CTR=0 MEM_LOAD_RETIRED.L1D_LINE_MISS
+CB.04.CTR=0 MEM_LOAD_RETIRED.L2_MISS
+CB.08.CTR=0 MEM_LOAD_RETIRED.L2_LINE_MISS
+40.08 L1D_CACHE_LD.M
+40.04 L1D_CACHE_LD.E
+40.02 L1D_CACHE_LD.S
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