mirror of
https://github.com/andreas-abel/nanoBench.git
synced 2025-12-16 11:30:07 +01:00
support for indexed addressing modes
This commit is contained in:
Andreas Abel
@@ -37,8 +37,8 @@ instrNodeList = [] # list of all XML instruction nodes that are not filtered out
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instrNodeDict = {} # dict from instrNode.attrib['string'] to instrNode
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globalDoNotWriteRegs = {'R13', 'R13D', 'R13W', 'R13B', 'R14', 'R14D', 'R14W', 'R14B', 'R15', 'R15D', 'R15W', 'R15B', 'SP', 'SPL', 'ESP', 'RSP', 'XMM13', 'YMM13', 'ZMM13', 'XMM14', 'YMM14', 'ZMM14', 'XMM15', 'YMM15', 'ZMM15', 'MM15', 'IP', 'DR4', 'DR5', 'DR6', 'DR7', 'RBP', 'EBP', 'BP', 'K0'} #ToDo
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#R14: reserved for memory addresses
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#R13: can be written in init; will not be overwritten by other code
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#R14: reserved for memory addresses (base)
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#R13: reserved for memory addresses (index)
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#R15: loop counter
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specialRegs = {'ES', 'CS', 'SS', 'DS', 'FS', 'GS', 'IP', 'EIP', 'FSBASEy', 'GDTR', 'GSBASEy', 'IDTR', 'IP', 'LDTR', 'MSRS', 'MXCSR', 'RFLAGS', 'RIP',
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@@ -60,7 +60,6 @@ def isIntelCPU():
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return not isAMDCPU()
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def getAddrReg(instrNode, opNode):
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if opNode.attrib.get('suppressed', '0') == '1':
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return opNode.attrib['base']
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@@ -69,6 +68,14 @@ def getAddrReg(instrNode, opNode):
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else:
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return 'R14'
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def getIndexReg(instrNode, opNode):
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if opNode.attrib.get('VSIB', '0') != '0':
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return opNode.attrib.get('VSIB') + '14'
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elif instrNode.attrib.get('rex', '1') == '0':
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return 'RSI'
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else:
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return 'R13'
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# registers that are not used as implicit registers should come first; RAX (and parts of it) should come last, as some instructions have special encodings for that
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# prefer low registers to high registers
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def sortRegs(regsList):
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@@ -76,7 +83,7 @@ def sortRegs(regsList):
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# Initialize registers and memory
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def getRegMemInit(instrNode, opRegDict, memOffset):
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def getRegMemInit(instrNode, opRegDict, memOffset, useIndexedAddr):
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iform = instrNode.attrib['iform']
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iclass = instrNode.attrib['iclass']
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@@ -124,13 +131,18 @@ def getRegMemInit(instrNode, opRegDict, memOffset):
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elif 'MM' in regPrefix:
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init += ['PXOR '+reg+', '+reg]
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elif opNode.attrib['type'] == 'mem':
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if 'VSIB' in opNode.attrib:
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vsibReg = opNode.attrib['VSIB'] + '14'
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init += ['VXORPS ' + vsibReg + ', ' + vsibReg + ', ' + vsibReg]
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if xtype.startswith('f'):
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init += ['MOV RAX, 0x4000000040000000']
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for i in range(0, int(opNode.attrib['width'])/8, 8): init += ['MOV [R14+' + str(i+memOffset) + '], RAX']
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for opNode in instrNode.findall('./operand[@type="mem"]'):
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if opNode.attrib.get('suppressed', '0') == '1': continue
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if 'VSIB' in opNode.attrib:
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vsibReg = getIndexReg(instrNode, opNode)
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init += ['VXORPS ' + vsibReg + ', ' + vsibReg + ', ' + vsibReg]
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elif useIndexedAddr:
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init += ['XOR {0}, {0}'.format(getIndexReg(instrNode, opNode))]
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return init
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nExperiments = 0
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@@ -144,7 +156,6 @@ def runExperiment(instrNode, instrCode, init=None, unrollCount=500, loopCount=0,
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nExperiments += 1
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instrCode = re.sub(';+', '; ', instrCode.strip('; '))
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if debugOutput: print 'instr: ' + instrCode
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codeObjFile = '/tmp/ramdisk/code.o'
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assemble(instrCode, codeObjFile, asmFile='/tmp/ramdisk/code.s')
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localHtmlReports.append('<li>Code: <pre>' + getMachineCode(codeObjFile) + '</pre></li>\n')
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@@ -178,6 +189,7 @@ def runExperiment(instrNode, instrCode, init=None, unrollCount=500, loopCount=0,
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nanoBenchCmd += ' -asm_init "' + initCode + '"'
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localHtmlReports.append('<li><a href="javascript:;" onclick="this.outerHTML = \'<pre>' + nanoBenchCmd + '</pre>\'">Show nanoBench command</a></li>\n')
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if debugOutput: print nanoBenchCmd
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setNanoBenchParameters(unrollCount=unrollCount, loopCount=loopCount, warmUpCount=warmUpCount, basicMode=basicMode)
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@@ -313,7 +325,8 @@ def configurePFCs(events):
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InstrInstance = namedtuple('InstrInstance', ['instrNode', 'asm', 'readRegs', 'writtenRegs', 'opRegDict', 'regMemInit'])
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def getInstrInstanceFromNode(instrNode, doNotWriteRegs=None, doNotReadRegs=None, useDistinctRegs=True, opRegDict=None, memOffset=0, immediate=2, computeRegMemInit=True):
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def getInstrInstanceFromNode(instrNode, doNotWriteRegs=None, doNotReadRegs=None, useDistinctRegs=True, opRegDict=None, memOffset=0, immediate=2,
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computeRegMemInit=True, useIndexedAddr=False):
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if not doNotWriteRegs: doNotWriteRegs = []
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if not doNotReadRegs: doNotReadRegs = []
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if not opRegDict: opRegDict = {}
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@@ -394,14 +407,12 @@ def getInstrInstanceFromNode(instrNode, doNotWriteRegs=None, doNotReadRegs=None,
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if asmprefix != '':
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asm += ' '
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address = ''
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if operandNode.attrib.get('VSIB', '0') != "0":
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address = 'R14+' + operandNode.attrib.get('VSIB') + '14'
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readRegs.add('R14')
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readRegs.add(operandNode.attrib.get('VSIB') + '14')
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else:
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address = getAddrReg(instrNode, operandNode)
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readRegs.add(address)
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if useIndexedAddr or operandNode.attrib.get('VSIB', '0') != '0':
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indexReg = getIndexReg(instrNode, operandNode)
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address += '+' + indexReg
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readRegs.add(indexReg)
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asm += '[' + address + ('+'+str(memOffset) if memOffset else '') + ']'
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@@ -444,7 +455,7 @@ def getInstrInstanceFromNode(instrNode, doNotWriteRegs=None, doNotReadRegs=None,
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asm = asm + '; 1: '
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regMemInit = []
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if computeRegMemInit: regMemInit = getRegMemInit(instrNode, opRegDict, memOffset)
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if computeRegMemInit: regMemInit = getRegMemInit(instrNode, opRegDict, memOffset, useIndexedAddr)
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return InstrInstance(instrNode, asm, readRegs, writtenRegs, opRegDict, regMemInit)
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def createIacaAsmFile(fileName, prefixInstr, prefixRep, instr):
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@@ -465,7 +476,7 @@ def getUopsOnBlockedPorts(instrNode, useDistinctRegs, blockInstrNode, blockInstr
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writtenRegs = instrInstance.writtenRegs
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if debugOutput: print ' instr: ' + instr + 'rR: ' + str(readRegs) + ', wR: ' + str(writtenRegs)
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blockInstrsList = getIndependentInstructions(blockInstrNode, True, writtenRegs|readRegs, writtenRegs|readRegs, 64)
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blockInstrsList = getIndependentInstructions(blockInstrNode, True, False, writtenRegs|readRegs, writtenRegs|readRegs, 64)
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if debugOutput: print ' bIL: ' + str(blockInstrsList)
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htmlReports.append('<hr><h3>With blocking instructions for port' +
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@@ -552,7 +563,7 @@ def getUopsOnBlockedPorts(instrNode, useDistinctRegs, blockInstrNode, blockInstr
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# Takes an instrNode and returns a list [instrI, instrI', ...] s.t. instrI(')* are the results of
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# calls to getInstrInstanceFromNode for instrNode and there are no read-after-writes of the same regs/memory locations. The length of the list is limited by maxTPRep.
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def getIndependentInstructions(instrNode, useDistinctRegs, doNotReadRegs = None, doNotWriteRegs = None, initialOffset = 0, immediate = 2):
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def getIndependentInstructions(instrNode, useDistinctRegs, useIndexedAddr, doNotReadRegs=None, doNotWriteRegs=None, initialOffset=0, immediate=2):
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if not doNotReadRegs: doNotReadRegs = set()
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if not doNotWriteRegs: doNotWriteRegs = set()
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doNotReadRegs |= specialRegs
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@@ -573,7 +584,7 @@ def getIndependentInstructions(instrNode, useDistinctRegs, doNotReadRegs = None,
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offset = initialOffset
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for _ in range(maxTPRep):
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instrI = getInstrInstanceFromNode(instrNode, doNotWriteRegs, doNotReadRegs, useDistinctRegs, {}, offset, immediate=immediate)
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instrI = getInstrInstanceFromNode(instrNode, doNotWriteRegs, doNotReadRegs, useDistinctRegs, {}, offset, immediate=immediate, useIndexedAddr=useIndexedAddr)
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if not instrI:
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break
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@@ -591,7 +602,7 @@ def getIndependentInstructions(instrNode, useDistinctRegs, doNotReadRegs = None,
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doNotReadRegs = doNotReadRegs | instrI.writtenRegs
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if not independentInstructions:
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instrI = getInstrInstanceFromNode(instrNode, useDistinctRegs=False, immediate=immediate)
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instrI = getInstrInstanceFromNode(instrNode, useDistinctRegs=False, immediate=immediate, useIndexedAddr=useIndexedAddr)
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independentInstructions.append(instrI)
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return independentInstructions
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@@ -611,6 +622,12 @@ def hasCommonRegister(instrNode):
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return True
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return False
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def hasExplicitNonVSIBMemOperand(instrNode):
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for opNode in instrNode.findall('./operand[@type="mem"]'):
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if opNode.attrib.get('suppressed', '') != '1' and opNode.attrib.get('VSIB', '0') == '0':
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return True
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return False
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def getThroughputIacaNoInteriteration(instrNode, htmlReports):
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createIacaAsmFile("/tmp/ramdisk/asm.s", "", 0, getInstrInstanceFromNode(instrNode, useDistinctRegs=True).asm)
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try:
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@@ -642,7 +659,7 @@ class TPConfig:
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self.preInstrNodes = ([] if preInstrNodes is None else preInstrNodes)
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self.note = note
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def getTPConfigs(instrNode, useDistinctRegs=True, computeIndepAndDepBreakingInstrs=True):
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def getTPConfigs(instrNode, useDistinctRegs=True, useIndexedAddr=False, computeIndepAndDepBreakingInstrs=True):
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iform = instrNode.attrib['iform']
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iclass = instrNode.attrib['iclass']
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@@ -652,7 +669,7 @@ def getTPConfigs(instrNode, useDistinctRegs=True, computeIndepAndDepBreakingInst
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independentInstrs = []
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depBreakingInstrs = ''
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if computeIndepAndDepBreakingInstrs:
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independentInstrs = getIndependentInstructions(instrNode, useDistinctRegs)
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independentInstrs = getIndependentInstructions(instrNode, useDistinctRegs, useIndexedAddr)
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depBreakingInstrs = getDependencyBreakingInstrsForSuppressedOperands(instrNode)
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# instructions with multiple configs
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@@ -662,7 +679,7 @@ def getTPConfigs(instrNode, useDistinctRegs=True, computeIndepAndDepBreakingInst
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if instrNode.attrib['string'].replace('I8', str(immediate)) in instrNodeDict:
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continue
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config = TPConfig(note='With immediate = ' + str(immediate))
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config.independentInstrs = getIndependentInstructions(instrNode, useDistinctRegs, immediate=immediate)
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config.independentInstrs = getIndependentInstructions(instrNode, useDistinctRegs, useIndexedAddr, immediate=immediate)
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config.depBreakingInstrs = depBreakingInstrs
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configs.append(config)
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return configs
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@@ -708,7 +725,7 @@ def getTPConfigs(instrNode, useDistinctRegs=True, computeIndepAndDepBreakingInst
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if iclass == 'FXRSTOR64': config.init = ['FXSAVE64 [R14]']
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if iform in ['IN_AL_IMMb', 'IN_OeAX_IMMb', 'OUT_IMMb_AL', 'OUT_IMMb_OeAX']:
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config.independentInstrs = getIndependentInstructions(instrNode, useDistinctRegs, immediate=0x80)
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config.independentInstrs = getIndependentInstructions(instrNode, useDistinctRegs, useIndexedAddr, immediate=0x80)
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if iform in ['IN_AL_DX', 'IN_OeAX_DX', 'OUT_DX_AL', 'OUT_DX_OeAX'] or instrNode.attrib['category'] in ['IOSTRINGOP']:
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config.init = ['mov DX, 0x80']
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@@ -905,8 +922,8 @@ TPResult = namedtuple('TPResult', ['TP', 'TP_noDepBreaking_noLoop', 'TP_single',
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# returns TPResult
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# port usages are averages (when no ports are blocked by other instructions)
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def getThroughputAndUops(instrNode, useDistinctRegs, htmlReports):
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configs = getTPConfigs(instrNode, useDistinctRegs)
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def getThroughputAndUops(instrNode, useDistinctRegs, useIndexedAddr, htmlReports):
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configs = getTPConfigs(instrNode, useDistinctRegs, useIndexedAddr)
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minTP = sys.maxint
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minTP_noDepBreaking_noLoop = sys.maxint
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@@ -1199,7 +1216,7 @@ def getDependencyBreakingInstrs(instrNode, opRegDict, ignoreOperand = None):
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if not (opNode.attrib.get('r', '') == '1' or opNode.attrib.get('conditionalWrite', '') == '1'): continue
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if not any(('flag_'+f in opNode.attrib) for f in STATUSFLAGS_noAF): continue
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depBreakingInstrs[opNode] = 'TEST R13, R13'
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depBreakingInstrs[opNode] = 'TEST R15, R15'
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return depBreakingInstrs
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@@ -1237,7 +1254,7 @@ def getDependencyBreakingInstrsForSuppressedOperands(instrNode):
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# on some CPUs, instructions that write flags conditionally also read the flags
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if not (opNode.attrib.get('r', '') == '1' or opNode.attrib.get('conditionalWrite', '') == '1'): continue
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if not any(('flag_'+f in opNode.attrib) for f in STATUSFLAGS_noAF): continue
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depBreakingInstrs += ['TEST R13, R13']
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depBreakingInstrs += ['TEST R15, R15']
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return ';'.join(depBreakingInstrs)
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@@ -1858,10 +1875,10 @@ def getLatConfigLists(instrNode, startNode, targetNode, useDistinctRegs, addrMem
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configList.append(LatConfig(instrI, chainInstrs=chainInstrs, chainLatency=chainLatency))
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elif 'MM' in reg:
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instrI = getInstrInstanceFromNode(instrNode, ['R13', 'R15'], ['R13', 'R15'], True, {startNodeIdx:reg})
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instrI = getInstrInstanceFromNode(instrNode, ['R12', 'R15'], ['R12', 'R15'], True, {startNodeIdx:reg})
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configList.isUpperBound = True
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for chainInstrI in getAllChainInstrsFromRegToReg(instrNode, 'R13', reg):
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chainInstrs = 'CMOV' + flag[0] + ' R13, R15; ' + chainInstrI.asm
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for chainInstrI in getAllChainInstrsFromRegToReg(instrNode, 'R12', reg):
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chainInstrs = 'CMOV' + flag[0] + ' R12, R15; ' + chainInstrI.asm
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chainLatency = basicLatency['CMOV' + flag[0]] + 1
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configList.append(LatConfig(instrI, chainInstrs=chainInstrs, chainLatency=chainLatency))
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elif targetNode.attrib['type'] == 'mem':
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@@ -1952,6 +1969,7 @@ def getLatConfigLists(instrNode, startNode, targetNode, useDistinctRegs, addrMem
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return None
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addrReg = getAddrReg(instrNode, startNode)
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indexReg = getIndexReg(instrNode, startNode)
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memWidth = int(startNode.attrib.get('width', 0))
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if targetNode.attrib['type'] == 'reg':
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@@ -1969,13 +1987,15 @@ def getLatConfigLists(instrNode, startNode, targetNode, useDistinctRegs, addrMem
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print 'read from suppressed mem to non-GPR reg not yet supported'
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return None
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if reg in GPRegs:
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instrI = getInstrInstanceFromNode(instrNode, [addrReg, 'R12'], [addrReg, 'R12'], useDistinctRegs, {targetNodeIdx:reg})
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instrI = getInstrInstanceFromNode(instrNode, [addrReg, indexReg, 'R12'], [addrReg, indexReg, 'R12'], useDistinctRegs, {targetNodeIdx:reg},
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useIndexedAddr=(addrMem=='addr_index'))
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if addrMem == 'addr':
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if reg in GPRegs:
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if addrMem in ['addr', 'addr_index']:
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# addr -> reg
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chainReg = (addrReg if addrMem == 'addr' else indexReg)
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chainInstrs = 'MOVSX ' + regTo64(reg) + ', ' + regToSize(reg, min(32, regSize)) + ';'
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chainInstrs += 'XOR {}, {};'.format(addrReg, regTo64(reg)) * cRep + ('TEST R13, R13;' if instrReadsFlags else '') # cRep is a multiple of 2
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chainInstrs += 'XOR {}, {};'.format(chainReg, regTo64(reg)) * cRep + ('TEST R15, R15;' if instrReadsFlags else '') # cRep is a multiple of 2
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chainLatency = basicLatency['MOVSX'] + basicLatency['XOR'] * cRep
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configList.append(LatConfig(instrI, chainInstrs=chainInstrs, chainLatency=chainLatency))
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else:
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@@ -1989,15 +2009,14 @@ def getLatConfigLists(instrNode, startNode, targetNode, useDistinctRegs, addrMem
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chainLatency += int(basicLatency['MOV_10MOVSX_MOV_'+str(regSize)] >= 12) # 0 if CPU supports zero-latency store forwarding
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configList.append(LatConfig(instrI, chainInstrs=chainInstrs, chainLatency=chainLatency))
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elif 'MM' in reg:
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instrI = getInstrInstanceFromNode(instrNode, ['R12'], ['R12'], useDistinctRegs, {targetNodeIdx:reg})
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if addrMem == 'addr':
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if addrMem in ['addr', 'addr_index']:
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# addr -> reg
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configList.isUpperBound = True
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chainReg = (addrReg if addrMem == 'addr' else indexReg)
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chainInstrs = 'MOVQ R12, {};'.format(getCanonicalReg(reg))
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if isAVXInstr(instrNode):
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chainInstrs = 'V' + chainInstrs
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chainInstrs += 'XOR {}, {};'.format(addrReg, 'R12') * cRep + ('TEST R13, R13;' if instrReadsFlags else '') # cRep is a multiple of 2
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chainInstrs += 'XOR {}, {};'.format(chainReg, 'R12') * cRep + ('TEST R15, R15;' if instrReadsFlags else '') # cRep is a multiple of 2
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chainLatency = 1 + basicLatency['XOR'] * cRep
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configList.append(LatConfig(instrI, chainInstrs=chainInstrs, chainLatency=chainLatency))
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elif addrMem == 'addr_VSIB':
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@@ -2018,11 +2037,13 @@ def getLatConfigLists(instrNode, startNode, targetNode, useDistinctRegs, addrMem
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if not ('flag_'+flag) in targetNode.attrib: continue
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if not 'w' in targetNode.attrib[('flag_'+flag)]: continue
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instrI = getInstrInstanceFromNode(instrNode, [addrReg, 'R12'], [addrReg, 'R12'], useDistinctRegs)
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instrI = getInstrInstanceFromNode(instrNode, [addrReg, indexReg, 'R12'], [addrReg, indexReg, 'R12'], useDistinctRegs,
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useIndexedAddr=(addrMem=='addr_index'))
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if addrMem == 'addr':
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if addrMem in ['addr', 'addr_index']:
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# addr -> flag
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chainInstr = 'CMOV' + flag[0] + ' ' + addrReg + ', ' + addrReg
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chainReg = (addrReg if addrMem == 'addr' else indexReg)
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chainInstr = 'CMOV' + flag[0] + ' ' + chainReg + ', ' + chainReg
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chainLatency = basicLatency['CMOV' + flag[0]]
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configList.append(LatConfig(instrI, chainInstrs=chainInstr, chainLatency=chainLatency))
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else:
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@@ -2043,14 +2064,17 @@ def getLatConfigLists(instrNode, startNode, targetNode, useDistinctRegs, addrMem
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# mem -> mem
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#################
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if startNode == targetNode:
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instrI = getInstrInstanceFromNode(instrNode, [addrReg, 'R12'], [addrReg, 'R12'], useDistinctRegs=useDistinctRegs)
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instrI = getInstrInstanceFromNode(instrNode, [addrReg, indexReg, 'R12'], [addrReg, indexReg, 'R12'], useDistinctRegs=useDistinctRegs,
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||||
useIndexedAddr=(addrMem=='addr_index'))
|
||||
|
||||
if addrMem == 'addr':
|
||||
if addrMem in ['addr', 'addr_index']:
|
||||
# addr -> mem
|
||||
configList.isUpperBound = True
|
||||
chainInstrs = 'MOV ' + regToSize('R12', min(64, memWidth)) + ', [' + addrReg + '];'
|
||||
chainReg = (addrReg if addrMem == 'addr' else indexReg)
|
||||
memStr = addrReg + ('+'+indexReg if addrMem == 'addr_index' else '')
|
||||
chainInstrs = 'MOV ' + regToSize('R12', min(64, memWidth)) + ', [' + memStr + '];'
|
||||
chainInstrs += ('MOVSX R12, ' + regToSize('R12', min(32, memWidth)) + ';') * cRep
|
||||
chainInstrs += 'XOR ' + addrReg + ', R12; XOR ' + addrReg + ', R12;' + ('TEST R13, R13;' if instrReadsFlags else '')
|
||||
chainInstrs += 'XOR ' + chainReg + ', R12; XOR ' + chainReg + ', R12;' + ('TEST R15, R15;' if instrReadsFlags else '')
|
||||
chainLatency = basicLatency['MOVSX'] * cRep + 2*basicLatency['XOR']
|
||||
chainLatency += int(basicLatency['MOV_10MOVSX_MOV_'+str(min(64, memWidth))] >= 12) # 0 if CPU supports zero-latency store forwarding
|
||||
configList.append(LatConfig(instrI, chainInstrs=chainInstrs, chainLatency=chainLatency))
|
||||
@@ -2144,9 +2168,18 @@ def getLatencies(instrNode, instrNodeList, tpDict, htmlReports):
|
||||
|
||||
addrMemList = ['']
|
||||
if opNode1.attrib['type']=='mem':
|
||||
addrMemList = ['addr', 'mem']+(['addr_VSIB'] if 'VSIB' in opNode1.attrib else [])
|
||||
elif opNode1.attrib['type']=='agen' and ('B' in instrNode.attrib['agen'] or 'I' in instrNode.attrib['agen']):
|
||||
addrMemList = ['addr']
|
||||
if 'VSIB' in opNode1.attrib:
|
||||
addrMemList.append('addr_VSIB')
|
||||
elif opNode1.attrib.get('suppressed', '') != '1':
|
||||
addrMemList.append('addr_index')
|
||||
addrMemList.append('mem') # mem added last; order is relevant for html output
|
||||
elif opNode1.attrib['type']=='agen' and ('B' in instrNode.attrib['agen'] or 'I' in instrNode.attrib['agen']):
|
||||
addrMemList = []
|
||||
if 'B' in instrNode.attrib['agen']:
|
||||
addrMemList.append('addr')
|
||||
if 'I' in instrNode.attrib['agen']:
|
||||
addrMemList.append('addr_index')
|
||||
|
||||
for addrMem in addrMemList:
|
||||
minLatDistinctRegs = 0
|
||||
@@ -2613,17 +2646,19 @@ def main():
|
||||
|
||||
tpDict = {}
|
||||
tpDictSameReg = {}
|
||||
tpDictIndexedAddr = {}
|
||||
tpDictNoInteriteration = {}
|
||||
|
||||
if args.tpInput is not None:
|
||||
with open(args.tpInput, 'rb') as f:
|
||||
pTpDict, pTpDictSameReg, pTpDictNoInteriteration = pickle.load(f)
|
||||
pTpDict, pTpDictSameReg, pTpDictIndexedAddr, pTpDictNoInteriteration = pickle.load(f)
|
||||
tpDict = {instrNodeDict[k.attrib['string']]:v for k,v in pTpDict.items()}
|
||||
tpDictSameReg = {instrNodeDict[k.attrib['string']]:v for k,v in pTpDictSameReg.items()}
|
||||
tpDictIndexedAddr = {instrNodeDict[k.attrib['string']]:v for k,v in pTpDictIndexedAddr.items()}
|
||||
tpDictNoInteriteration = {instrNodeDict[k.attrib['string']]:v for k,v in pTpDictNoInteriteration.items()}
|
||||
else:
|
||||
for i, instrNode in enumerate(instrNodeList):
|
||||
#if not 'MOVZX_NOREX' in instrNode.attrib['string']: continue
|
||||
#if not 'MOV_NOREX' in instrNode.attrib['string']: continue
|
||||
print 'Measuring throughput for ' + instrNode.attrib['string'] + ' (' + str(i) + '/' + str(len(instrNodeList)) + ')'
|
||||
|
||||
htmlReports = ['<h1>' + instrNode.attrib['string'] + ' - Throughput and Uops' + (' (IACA '+iacaVersion+')' if useIACA else '') + '</h1>\n<hr>\n']
|
||||
@@ -2631,7 +2666,10 @@ def main():
|
||||
hasCommonReg = hasCommonRegister(instrNode)
|
||||
if hasCommonReg: htmlReports.append('<h2 id="distinctRegs">With different registers for different operands</h2>\n')
|
||||
|
||||
tpResult = getThroughputAndUops(instrNode, True, htmlReports)
|
||||
hasExplMemOp = hasExplicitNonVSIBMemOperand(instrNode)
|
||||
if hasExplMemOp: htmlReports.append('<h2 id="nonIndexedAddr">With a non-indexed addressing mode</h2>\n')
|
||||
|
||||
tpResult = getThroughputAndUops(instrNode, True, False, htmlReports)
|
||||
print instrNode.attrib['string'] + " - tp: " + str(tpResult)
|
||||
|
||||
if tpResult:
|
||||
@@ -2639,10 +2677,16 @@ def main():
|
||||
|
||||
if hasCommonReg:
|
||||
htmlReports.append('<hr><h2 id="sameReg">With the same register for for different operands</h2>\n')
|
||||
tpResultSameReg = getThroughputAndUops(instrNode, False, htmlReports)
|
||||
tpResultSameReg = getThroughputAndUops(instrNode, False, False, htmlReports)
|
||||
if tpResultSameReg:
|
||||
tpDictSameReg[instrNode] = tpResultSameReg
|
||||
|
||||
if hasExplMemOp:
|
||||
htmlReports.append('<hr><h2 id="indexedAddr">With an indexed addressing mode</h2>\n')
|
||||
tpResultIndexed = getThroughputAndUops(instrNode, True, True, htmlReports)
|
||||
if tpResultIndexed:
|
||||
tpDictIndexedAddr[instrNode] = tpResultIndexed
|
||||
|
||||
if useIACA and iacaVersion in ['2.1', '2.2']:
|
||||
htmlReports.append('<hr><h2 id="noInteriteration">With the -no_interiteration flag</h2>\n')
|
||||
tp = getThroughputIacaNoInteriteration(instrNode, htmlReports)
|
||||
@@ -2650,7 +2694,7 @@ def main():
|
||||
|
||||
if tpResult: writeHtmlFile('html-tp/'+arch, instrNode, instrNode.attrib['string'], ''.join(htmlReports))
|
||||
with open('tp_' + arch + '.pickle', 'wb') as f:
|
||||
pickle.dump((tpDict, tpDictSameReg, tpDictNoInteriteration), f)
|
||||
pickle.dump((tpDict, tpDictSameReg, tpDictIndexedAddr, tpDictNoInteriteration), f)
|
||||
|
||||
num_ports = len(tpDict.values()[0].unblocked_ports)
|
||||
|
||||
@@ -2669,7 +2713,7 @@ def main():
|
||||
latencyDict = {instrNodeDict[k.attrib['string']]:v for k,v in pickle.load(f).items()}
|
||||
elif not useIACA or iacaVersion == '2.1':
|
||||
for i, instrNode in enumerate(instrNodeList):
|
||||
#if not 'LEA' in instrNode.attrib['string']: continue
|
||||
#if not 'ADC' in instrNode.attrib['string']: continue
|
||||
print 'Measuring latencies for ' + instrNode.attrib['string'] + ' (' + str(i) + '/' + str(len(instrNodeList)) + ')'
|
||||
|
||||
htmlReports = ['<h1>' + instrNode.attrib['string'] + ' - Latency' + (' (IACA '+iacaVersion+')' if useIACA else '') + '</h1>\n<hr>\n']
|
||||
@@ -2692,6 +2736,7 @@ def main():
|
||||
# the elements of this set are sets of ports that either have the same functional units, or that cannot be used independently
|
||||
portCombinationsResultDict = {}
|
||||
portCombinationsResultDictSameReg = {}
|
||||
portCombinationsResultDictIndexedAddr = {}
|
||||
|
||||
if not args.noPorts:
|
||||
# iforms of instructions that are potentially zero-latency instructions
|
||||
@@ -2791,7 +2836,7 @@ def main():
|
||||
|
||||
for i, instrNode in enumerate(instrNodeList):
|
||||
if not instrNode in tpDict:
|
||||
# don't iterate over the keys of unblocked_ports_dict directly because of the ordering
|
||||
# don't iterate over the keys of tpDict directly because of the ordering
|
||||
continue
|
||||
|
||||
print 'Measuring port usage for ' + instrNode.attrib['string'] + ' (' + str(i) + '/' + str(len(instrNodeList)) + ')'
|
||||
@@ -2799,15 +2844,20 @@ def main():
|
||||
htmlReports = ['<h1>' + instrNode.attrib['string'] + ' - Port Usage' + (' (IACA '+iacaVersion+')' if useIACA else '') + '</h1>']
|
||||
|
||||
for useDistinctRegs in ([True, False] if instrNode in tpDictSameReg else [True]):
|
||||
|
||||
for useIndexedAddr in ([False, True] if useDistinctRegs and (instrNode in tpDictIndexedAddr) else [False]):
|
||||
tpResult = None
|
||||
|
||||
if useDistinctRegs:
|
||||
tpResult = tpDict[instrNode]
|
||||
if not useDistinctRegs:
|
||||
tp1 = tpDict[instrNode]
|
||||
tp2 = tpDictSameReg[instrNode]
|
||||
if (tp1.uops == tp2.uops and tp1.fused_uops == tp2.fused_uops): continue
|
||||
tpResult = tp2
|
||||
htmlReports.append('<hr><h2>With the same register for different operands</h2>')
|
||||
elif useIndexedAddr:
|
||||
tpResult = tpDictIndexedAddr[instrNode]
|
||||
htmlReports.append('<hr><h2>With an indexed addressing mode</h2>')
|
||||
else:
|
||||
if tpDict[instrNode].uops == tpDictSameReg[instrNode].uops: continue
|
||||
tpResult = tpDictSameReg[instrNode]
|
||||
htmlReports.append('<h2>With the same register for different operands</h2>')
|
||||
tpResult = tpDict[instrNode]
|
||||
|
||||
rem_uops = max(tpResult.uops, int(sum(x for p, x in tpResult.unblocked_ports.items() if x>0) + .2))
|
||||
|
||||
@@ -2885,10 +2935,13 @@ def main():
|
||||
# we split these combinations now, as, e.g., the call to getTP_LP requires them to be separate
|
||||
uopsCombinationList = [(frozenset(''.join(map(str,comb))), uops) for comb, uops in uopsCombinationList]
|
||||
|
||||
if useDistinctRegs:
|
||||
portCombinationsResultDict[instrNode] = uopsCombinationList
|
||||
else:
|
||||
if not useDistinctRegs:
|
||||
portCombinationsResultDictSameReg[instrNode] = uopsCombinationList
|
||||
elif useIndexedAddr:
|
||||
portCombinationsResultDictIndexedAddr[instrNode] = uopsCombinationList
|
||||
else:
|
||||
portCombinationsResultDict[instrNode] = uopsCombinationList
|
||||
|
||||
|
||||
writeHtmlFile('html-ports/'+arch, instrNode, instrNode.attrib['string'], ''.join(htmlReports))
|
||||
|
||||
@@ -2905,13 +2958,18 @@ def main():
|
||||
else:
|
||||
resultNode = archNode.find('./measurement')
|
||||
|
||||
tpResult_dr = tpDict[instrNode]
|
||||
tpResult_sr = tpDictSameReg.get(instrNode, tpResult_dr)
|
||||
|
||||
for tpResult in ([tpResult_dr, tpResult_sr] if tpResult_dr.uops != tpResult_sr.uops else [tpResult_dr]):
|
||||
suffix = ('' if tpResult == tpResult_dr else '_same_reg')
|
||||
curPortCombinationsResultDict = (portCombinationsResultDict if tpResult == tpResult_dr else portCombinationsResultDictSameReg)
|
||||
applicableResults = [(tpDict[instrNode], portCombinationsResultDict.get(instrNode, None), '')]
|
||||
for otherTPDict, otherPCDict, suffix in [(tpDictSameReg, portCombinationsResultDictSameReg, '_same_reg'),
|
||||
(tpDictIndexedAddr, portCombinationsResultDictIndexedAddr, '_indexed')]:
|
||||
if instrNode in otherTPDict:
|
||||
t1 = tpDict[instrNode]
|
||||
t2 = otherTPDict[instrNode]
|
||||
p1 = portCombinationsResultDict.get(instrNode, None)
|
||||
p2 = otherPCDict.get(instrNode, None)
|
||||
if (t1.uops != t2.uops or t1.fused_uops != t2.fused_uops or ((p2 is not None) and (p1 != p2))):
|
||||
applicableResults.append((t2, p2, suffix))
|
||||
|
||||
for tpResult, portUsageList, suffix in applicableResults:
|
||||
uops = tpResult.uops
|
||||
uopsFused = tpResult.fused_uops
|
||||
if useIACA:
|
||||
@@ -2937,10 +2995,7 @@ def main():
|
||||
|
||||
portPrefix = ('p' if isIntelCPU() else 'FP')
|
||||
computePortStr = lambda lst: '+'.join(str(uops)+'*'+portPrefix+''.join(str(p) for p in sorted(c)) for c, uops in sorted(lst, key=lambda x: sorted(x[0])))
|
||||
if instrNode in curPortCombinationsResultDict:
|
||||
portUsageList = curPortCombinationsResultDict[instrNode]
|
||||
if not portUsageList: continue
|
||||
|
||||
if portUsageList:
|
||||
resultNode.attrib['ports'+suffix] = computePortStr(portUsageList)
|
||||
|
||||
portUsageWithDivList = list(portUsageList)
|
||||
|
||||
@@ -109,7 +109,7 @@ def latencyNodeToStr(latNode, sameReg, addr_mem):
|
||||
ret += ', with the same register for different operands'
|
||||
if addr_mem == 'addr':
|
||||
ret += ' (address, base register)'
|
||||
elif addr_mem == 'addr_VSIB':
|
||||
elif addr_mem in ['addr_index', 'addr_VSIB']:
|
||||
ret += ' (address, index register)'
|
||||
elif addr_mem == 'mem':
|
||||
ret += ' (memory)'
|
||||
@@ -144,7 +144,7 @@ def getLatencyTableEntry(measurementNode):
|
||||
|
||||
for latNode in measurementNode.findall('./latency'):
|
||||
for sameReg in [False, True]:
|
||||
for addr_mem in ['', 'addr', 'mem']:
|
||||
for addr_mem in ['', 'addr', 'addr_index', 'addr_VSIB', 'mem']:
|
||||
suffix = ('_'+addr_mem if addr_mem else '') + ('_same_reg' if sameReg else '')
|
||||
if 'cycles'+suffix in latNode.attrib:
|
||||
cycles = int(latNode.attrib['cycles'+suffix])
|
||||
|
||||
Reference in New Issue
Block a user