mirror of
https://github.com/andreas-abel/nanoBench.git
synced 2026-01-04 19:40:08 +01:00
update
This commit is contained in:
Andreas Abel
@@ -444,14 +444,17 @@ def getInstrInstanceFromNode(instrNode, doNotWriteRegs=None, doNotReadRegs=None,
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if asmprefix != '':
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asm += ' '
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address = getAddrReg(instrNode, operandNode)
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readRegs.add(address)
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if useIndexedAddr or operandNode.attrib.get('VSIB', '0') != '0':
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indexReg = getIndexReg(instrNode, operandNode)
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address += '+' + indexReg
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readRegs.add(indexReg)
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if operandNode.attrib.get('moffs', '0') == '1':
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asm += '[' + getAddress('R14') + ']'
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else:
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address = getAddrReg(instrNode, operandNode)
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readRegs.add(address)
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if useIndexedAddr or operandNode.attrib.get('VSIB', '0') != '0':
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indexReg = getIndexReg(instrNode, operandNode)
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address += '+' + indexReg
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readRegs.add(indexReg)
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asm += '[' + address + ('+'+str(memOffset) if memOffset else '') + ']'
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asm += '[' + address + ('+'+str(memOffset) if memOffset else '') + ']'
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memorySuffix = operandNode.attrib.get('memory-suffix', '')
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if memorySuffix:
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@@ -834,7 +837,7 @@ def getPreInstr(instrNode):
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if iform in ['CALL_NEAR_MEMv', 'JMP_MEMv']:
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preInstrCode = 'lea RAX, [RIP+6]; mov [R14], RAX'
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preInstrNodes = [instrNodeDict['LEA_R_D8 (R64)'], instrNodeDict['MOV (M64, RAX)']]
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preInstrNodes = [instrNodeDict['LEA_R_D8 (R64)'], instrNodeDict['MOV (M64, R64)']]
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if iform == 'LEAVE':
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preInstrCode = 'lea RBP, [R14]'
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@@ -850,11 +853,11 @@ def getPreInstr(instrNode):
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if iform == 'RET_NEAR':
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preInstrCode = 'lea RAX, [RIP+5]; mov [RSP], RAX'
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preInstrNodes = [instrNodeDict['LEA_R_D8 (R64)'], instrNodeDict['MOV (M64, RAX)']]
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preInstrNodes = [instrNodeDict['LEA_R_D8 (R64)'], instrNodeDict['MOV (M64, R64)']]
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if iform == 'RET_NEAR_IMMw':
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preInstrCode = 'lea RAX, [RIP+7]; mov [RSP], RAX'
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preInstrNodes = [instrNodeDict['LEA_R_D8 (R64)'], instrNodeDict['MOV (M64, RAX)']]
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preInstrNodes = [instrNodeDict['LEA_R_D8 (R64)'], instrNodeDict['MOV (M64, R64)']]
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return (preInstrCode, preInstrNodes)
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@@ -1252,15 +1255,18 @@ def canMacroFuse(flagInstrNode, branchInstrNode, htmlReports):
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basicLatency = {}
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def getBasicLatencies(instrNodeList):
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movsxResult = runExperiment(instrNodeDict['MOVSXD (R64, R32)'], 'MOVSX RAX, EAX')
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movsxCycles = int(round(movsxResult['Core cycles']))
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if movsxCycles != 1:
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print('Latency of MOVSX must be 1')
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sys.exit()
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basicLatency['MOVSX'] = movsxCycles
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for t in [16, 32, 64]:
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for s in [8,16,32]:
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if s >= t:
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continue
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movsxResult = runExperiment(None, 'MOVSX {}, {}'.format(regToSize('RAX', t), regToSize('RAX', s)))
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basicLatency['MOVSX_R{}_R{}'.format(t,s)] = int(round(movsxResult['Core cycles']))
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if t < 64:
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movsxResult = runExperiment(None, 'MOVSX {}, ah'.format(regToSize('RAX', t)))
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basicLatency['MOVSX_R{}_R8h'.format(t)] = int(round(movsxResult['Core cycles']))
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movsxR8hResult = runExperiment(None, 'MOV AH, AL')
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basicLatency['MOV_R8h_R8l'] = max(1, int(round(movsxR8hResult['Core cycles'])))
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movR8hResult = runExperiment(None, 'MOV AH, AL')
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basicLatency['MOV_R8h_R8l'] = max(1, int(round(movR8hResult['Core cycles'])))
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movR8hR8hResult = runExperiment(instrNodeDict['MOV_88 (R8h, R8h)'], 'MOV AH, AH')
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basicLatency['MOV_R8h_R8h'] = int(round(movR8hR8hResult['Core cycles']))
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@@ -1503,9 +1509,10 @@ def getDivLatConfigLists(instrNode, opNode1, opNode2, cRep):
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if opNode == opNode1:
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if opNode == divisorNode:
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if memDivisor:
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chainInstrs = 'MOVSX R12, ' + regToSize(opNode2.text, min(getRegSize(opNode2.text), 32)) + '; '
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reg2Size = min(getRegSize(opNode2.text), 32)
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chainInstrs = 'MOVSX R12, ' + regToSize(opNode2.text, reg2Size) + '; '
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chainInstrs += ('XOR R14, R12; ') * cRep # cRep is a power of two
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chainLatency = basicLatency['MOVSX'] + basicLatency['XOR'] * cRep
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chainLatency = basicLatency['MOVSX_R64_R' + str(reg2Size)] + basicLatency['XOR'] * cRep
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else:
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chainInstrs = 'AND {0}, {1}; AND {0}, {2}; OR {0}, {2}; '.format(divisorReg, regToSize(opNode2.text, getRegSize(divisorReg)),
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regToSize(immReg['divisor'], getRegSize(divisorReg)))
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@@ -1930,13 +1937,13 @@ def getLatConfigLists(instrNode, startNode, targetNode, useDistinctRegs, addrMem
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if startNode.text and targetNode.text and 'BP' in startNode.text and 'BP' in targetNode.text:
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chainInstrs = 'MOVSX RBP, BP; ' * cRep
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chainInstrs += 'AND RBP, R14; OR RBP, R14; '
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chainLatency = basicLatency['MOVSX'] * cRep + basicLatency['AND'] + basicLatency['OR']
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chainLatency = basicLatency['MOVSX_R64_R8'] * cRep + basicLatency['AND'] + basicLatency['OR']
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configList.append(LatConfig(getInstrInstanceFromNode(instrNode), chainInstrs=chainInstrs, chainLatency=chainLatency))
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elif startNode.text and targetNode.text and 'BP' in startNode.text and 'SP' in targetNode.text:
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chainInstrs = 'MOVSX RBP, SP; '
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chainInstrs += 'MOVSX RBP, BP; ' * cRep
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chainInstrs += 'AND RBP, R14; OR RBP, R14; '
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chainLatency = basicLatency['MOVSX'] + basicLatency['MOVSX'] * cRep + basicLatency['AND'] + basicLatency['OR']
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chainLatency = basicLatency['MOVSX_R64_R8'] + basicLatency['MOVSX_R64_R8'] * cRep + basicLatency['AND'] + basicLatency['OR']
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configList.append(LatConfig(getInstrInstanceFromNode(instrNode), chainInstrs=chainInstrs, chainLatency=chainLatency))
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else:
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return None
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@@ -1953,7 +1960,7 @@ def getLatConfigLists(instrNode, startNode, targetNode, useDistinctRegs, addrMem
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chainInstrs = 'MOVSX ECX, {}; '.format(regTo16(targetNode.text))
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chainInstrs += 'MOVSX ECX, CX; ' * cRep
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chainInstrs += 'AND ECX, 0; '
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chainLatency = basicLatency['MOVSX'] * (cRep + 1) + basicLatency['AND']
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chainLatency = basicLatency['MOVSX_R32_R16'] * (cRep + 1) + basicLatency['AND']
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configList.append(LatConfig(getInstrInstanceFromNode(instrNode), chainInstrs=chainInstrs, chainLatency=chainLatency))
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else:
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return None
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@@ -2026,18 +2033,24 @@ def getLatConfigLists(instrNode, startNode, targetNode, useDistinctRegs, addrMem
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chainInstrs += 'MOV {}, {};'.format(reg1, reg1) * cRep
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configList.append(LatConfig(instrI, chainInstrs=chainInstrs, chainLatency=basicLatency['MOV_R8h_R8l'] + basicLatency['MOV_R8h_R8h']*cRep))
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else:
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chainInstrs = 'MOVSX {}, {};'.format(regTo64(reg1), regToSize(reg2, min(32, getRegSize(reg2))))
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reg2Size = min(32, getRegSize(reg2))
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chainInstrs = 'MOVSX {}, {};'.format(regTo64(reg1), regToSize(reg2, reg2Size))
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chainInstrs += 'MOV {}, {};'.format(reg1, regTo8(reg1))
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chainInstrs += 'MOV {}, {};'.format(reg1, reg1) * cRep
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configList.append(LatConfig(instrI, chainInstrs=chainInstrs, chainLatency=basicLatency['MOVSX'] + basicLatency['MOV_R8h_R8l']
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+ basicLatency['MOV_R8h_R8h']*cRep))
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configList.append(LatConfig(instrI, chainInstrs=chainInstrs, chainLatency=basicLatency['MOVSX_R64_R'+str(reg2Size)]
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+ basicLatency['MOV_R8h_R8l'] + basicLatency['MOV_R8h_R8h']*cRep))
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else:
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# MOVSX avoids partial reg stalls and cannot be eliminated by "move elimination"
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reg1s = regTo32(reg1) if (reg2 in High8Regs) else regTo64(reg1)
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reg2s = reg2 if (reg2 in High8Regs) else regToSize(reg2, min(32, getRegSize(reg2)))
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chainInstrs = 'MOVSX {}, {};'.format(reg1s, reg2s)
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chainInstrs += 'MOVSX {}, {};'.format(regTo64(reg1), regTo32(reg1)) * cRep
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configList.append(LatConfig(instrI, chainInstrs=chainInstrs, chainLatency=basicLatency['MOVSX']*(cRep+1)))
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if reg2 in High8Regs:
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chainInstrs = 'MOVSX {}, {};'.format(regTo32(reg1), reg2)
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chainInstrs += 'MOVSX {}, {};'.format(regTo64(reg1), regTo32(reg1)) * cRep
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configList.append(LatConfig(instrI, chainInstrs=chainInstrs, chainLatency=basicLatency['MOVSX_R32_R8h'] + basicLatency['MOVSX_R64_R32']*cRep))
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else:
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reg2Size = min(32, getRegSize(reg2))
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chainInstrs = 'MOVSX {}, {};'.format(regTo64(reg1), regToSize(reg2, reg2Size))
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chainInstrs += 'MOVSX {}, {};'.format(regTo64(reg1), regTo32(reg1)) * cRep
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configList.append(LatConfig(instrI, chainInstrs=chainInstrs, chainLatency=basicLatency['MOVSX_R64_R'+str(reg2Size)]
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+ basicLatency['MOVSX_R64_R32']*cRep))
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elif reg1Prefix == 'K' and reg2Prefix == 'K':
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chainInstr = 'KMOVQ {}, {};'.format(reg1, reg2)
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chainInstr += 'KMOVQ {0}, {0};'.format(reg1) * cRep
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@@ -2100,8 +2113,9 @@ def getLatConfigLists(instrNode, startNode, targetNode, useDistinctRegs, addrMem
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chainLatency = basicLatency['SET' + flag[0]]
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else:
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chainInstr = 'CMOV{} {}, {};'.format(flag[0], regToSize('R15', regSize), regToSize('R15', regSize))
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chainInstr += 'MOVSX {}, {};'.format(regTo64(reg), regToSize('R15', min(32, regSize)))
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chainLatency = basicLatency['CMOV' + flag[0]] + basicLatency['MOVSX']
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r15Size = min(32, regSize)
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chainInstr += 'MOVSX {}, {};'.format(regTo64(reg), regToSize('R15', r15Size))
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chainLatency = basicLatency['CMOV' + flag[0]] + basicLatency['MOVSX_R64_R'+str(r15Size)]
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instrI = getInstrInstanceFromNode(instrNode, ['R15'], ['R15'], useDistinctRegs, {startNodeIdx:reg})
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if reg in High8Regs:
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@@ -2109,9 +2123,10 @@ def getLatConfigLists(instrNode, startNode, targetNode, useDistinctRegs, addrMem
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chainInstrs = chainInstr + movInstr * cRep
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chainLatency = chainLatency + basicLatency['MOV_R8h_R8h'] * cRep
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else:
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movsxInstr = 'MOVSX {}, {};'.format(regTo64(reg), regToSize(reg, min(32, regSize)))
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reg2Size = min(32, regSize)
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movsxInstr = 'MOVSX {}, {};'.format(regTo64(reg), regToSize(reg, reg2Size))
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chainInstrs = chainInstr + movsxInstr * cRep
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chainLatency = chainLatency + basicLatency['MOVSX'] * cRep
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chainLatency = chainLatency + basicLatency['MOVSX_R64_R'+str(reg2Size)] * cRep
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configList.append(LatConfig(instrI, chainInstrs=chainInstrs, chainLatency=chainLatency))
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elif 'MM' in reg:
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@@ -2139,8 +2154,9 @@ def getLatConfigLists(instrNode, startNode, targetNode, useDistinctRegs, addrMem
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chainInstrs += 'MOV {}, {};'.format(reg, reg) * cRep
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chainLatency = basicLatency['MOV_R8h_R8h'] * cRep
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else:
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chainInstrs += 'MOVSX {}, {};'.format(regTo64(reg), regToSize(reg, min(32, getRegSize(reg)))) * cRep
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chainLatency = basicLatency['MOVSX'] * cRep
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reg2Size = min(32, getRegSize(reg))
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chainInstrs += 'MOVSX {}, {};'.format(regTo64(reg), regToSize(reg, reg2Size)) * cRep
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chainLatency = basicLatency['MOVSX_R64_R'+str(reg2Size)] * cRep
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chainLatency += int(basicLatency['MOV_10MOVSX_MOV_'+str(getRegSize(reg))] >= 12) # 0 if CPU supports zero-latency store forwarding
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if re.search('BT.*MEMv_GPRv', instrNode.attrib['iform']):
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@@ -2190,8 +2206,9 @@ def getLatConfigLists(instrNode, startNode, targetNode, useDistinctRegs, addrMem
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chainInstrs = 'MOV {}, {};'.format(reg, reg) * cRep + chainInstrs
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chainLatency += basicLatency['MOV_R8h_R8h'] * cRep
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else:
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chainInstrs = 'MOVSX {}, {};'.format(regTo64(reg), regToSize(reg, min(32, getRegSize(reg)))) * cRep + chainInstrs
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chainLatency += basicLatency['MOVSX'] * cRep
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reg2Size = min(32, getRegSize(reg))
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chainInstrs = 'MOVSX {}, {};'.format(regTo64(reg), regToSize(reg, reg2Size)) * cRep + chainInstrs
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chainLatency += basicLatency['MOVSX_R64_R'+str(reg2Size)] * cRep
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configList.append(LatConfig(instrI, chainInstrs=chainInstrs, chainLatency=chainLatency))
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else:
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# ToDo: there is no instruction from flag to vector reg; the only non-GPR that is possible are ST(0) and X87STATUS
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@@ -2250,22 +2267,24 @@ def getLatConfigLists(instrNode, startNode, targetNode, useDistinctRegs, addrMem
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if addrMem in ['addr', 'addr_index']:
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# addr -> reg
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chainReg = (addrReg if addrMem == 'addr' else indexReg)
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chainInstrs = 'MOVSX ' + regTo64(reg) + ', ' + regToSize(reg, min(32, regSize)) + ';'
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reg2Size = min(32, regSize)
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chainInstrs = 'MOVSX ' + regTo64(reg) + ', ' + regToSize(reg, reg2Size) + ';'
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chainInstrs += 'XOR {}, {};'.format(chainReg, regTo64(reg)) * cRep + ('TEST R15, R15;' if instrReadsFlags else '') # cRep is a multiple of 2
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chainLatency = basicLatency['MOVSX'] + basicLatency['XOR'] * cRep
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chainLatency = basicLatency['MOVSX_R64_R'+str(reg2Size)] + basicLatency['XOR'] * cRep
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else:
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# mem -> reg
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configList = LatConfigList()
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configList.isUpperBound = True
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chainInstrs = 'MOVSX R12, {};'.format(regToSize(reg, min(32, regSize)))
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reg2Size = min(32, regSize)
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chainInstrs = 'MOVSX R12, {};'.format(regToSize(reg, reg2Size))
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chainInstrs += 'MOVSX R12, R12d;' * (cRep-1)
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chainInstrs += 'mov [{}], {};'.format(addrReg, regToSize('R12', regSize))
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chainLatency = basicLatency['MOVSX'] * cRep
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chainLatency = basicLatency['MOVSX_R64_R'+str(reg2Size)] + basicLatency['MOVSX_R64_R32'] * (cRep-1)
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chainLatency += int(basicLatency['MOV_10MOVSX_MOV_'+str(regSize)] >= 12) # 0 if CPU supports zero-latency store forwarding
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if reg in High8Regs:
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chainInstrs = 'MOVSX {}, {};'.format(regTo32(reg), reg) + chainInstrs
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chainInstrs += 'MOV {}, {}'.format(reg, reg) # 'clean' reg again; this is not on the critical path
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chainLatency += basicLatency['MOVSX']
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chainLatency += basicLatency['MOVSX_R32_R8h']
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configList.append(LatConfig(instrI, chainInstrs=chainInstrs, chainLatency=chainLatency))
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elif 'MM' in reg:
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if addrMem in ['addr', 'addr_index']:
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@@ -2312,7 +2331,7 @@ def getLatConfigLists(instrNode, startNode, targetNode, useDistinctRegs, addrMem
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chainInstrs = 'CMOV' + flag[0] + ' R12, R12;'
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chainInstrs += 'MOVSX R12, R12d;' * cRep
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chainInstrs += 'mov [' + addrReg + '], ' + regToSize('R12', memWidth)
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chainLatency = basicLatency['CMOV' + flag[0]] + basicLatency['MOVSX'] * cRep
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chainLatency = basicLatency['CMOV' + flag[0]] + basicLatency['MOVSX_R64_R32'] * cRep
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chainLatency += int(basicLatency['MOV_10MOVSX_MOV_'+str(memWidth)] >= 12) # 0 if CPU supports zero-latency store forwarding
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configList.append(LatConfig(instrI, chainInstrs=chainInstrs, chainLatency=chainLatency))
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else:
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@@ -2332,9 +2351,10 @@ def getLatConfigLists(instrNode, startNode, targetNode, useDistinctRegs, addrMem
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chainReg = (addrReg if addrMem == 'addr' else indexReg)
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memStr = addrReg + ('+'+indexReg if addrMem == 'addr_index' else '')
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chainInstrs = 'MOV ' + regToSize('R12', min(64, memWidth)) + ', [' + memStr + '];'
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chainInstrs += ('MOVSX R12, ' + regToSize('R12', min(32, memWidth)) + ';') * cRep
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reg2Size = min(32, memWidth)
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chainInstrs += ('MOVSX R12, ' + regToSize('R12', reg2Size) + ';') * cRep
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chainInstrs += 'XOR ' + chainReg + ', R12; XOR ' + chainReg + ', R12;' + ('TEST R15, R15;' if instrReadsFlags else '')
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chainLatency = basicLatency['MOVSX'] * cRep + 2*basicLatency['XOR']
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chainLatency = basicLatency['MOVSX_R64_R'+str(reg2Size)] * cRep + 2*basicLatency['XOR']
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chainLatency += int(basicLatency['MOV_10MOVSX_MOV_'+str(min(64, memWidth))] >= 12) # 0 if CPU supports zero-latency store forwarding
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# we use basicMode, as the measurements for these benchmarks are often not very stable, in particular on, e.g., HSW
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configList.append(LatConfig(instrI, chainInstrs=chainInstrs, chainLatency=chainLatency, basicMode=True))
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@@ -2409,7 +2429,8 @@ def getLatencies(instrNode, instrNodeList, tpDict, tpDictSameReg, htmlReports):
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outputOpnds.append(opNode)
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if opNode.attrib.get('r', '0') == '0':
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if opNode.attrib['type'] == 'mem':
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inputOpnds.append(opNode) # address of memory write
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if 'moffs' not in opNode.attrib:
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inputOpnds.append(opNode) # address of memory write
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elif opNode.attrib.get('conditionalWrite', '0') == '1':
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inputOpnds.append(opNode)
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elif opNode.attrib['type'] == 'reg':
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@@ -2437,11 +2458,12 @@ def getLatencies(instrNode, instrNodeList, tpDict, tpDictSameReg, htmlReports):
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addrMemList = ['']
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if opNode1.attrib['type']=='mem':
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addrMemList = ['addr']
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if 'VSIB' in opNode1.attrib:
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addrMemList.append('addr_VSIB')
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elif opNode1.attrib.get('suppressed', '') != '1':
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addrMemList.append('addr_index')
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if 'moffs' not in opNode1.attrib:
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addrMemList = ['addr']
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if 'VSIB' in opNode1.attrib:
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addrMemList.append('addr_VSIB')
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elif opNode1.attrib.get('suppressed', '') != '1':
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addrMemList.append('addr_index')
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addrMemList.append('mem') # mem added last; order is relevant for html output
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elif opNode1.attrib['type']=='agen' and ('B' in instrNode.attrib['agen'] or 'I' in instrNode.attrib['agen']):
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addrMemList = []
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@@ -2715,6 +2737,10 @@ def filterInstructions(XMLRoot):
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instrSet.discard(XMLInstr)
|
||||
if extension in ['MCOMMIT', 'WBNOINVD']: instrSet.discard(XMLInstr)
|
||||
|
||||
# Not supported any more by gnu as 2.36.1
|
||||
if (isaSet == 'MPX') and ('R' in XMLInstr.attrib.get('agen', '')):
|
||||
instrSet.discard(XMLInstr)
|
||||
|
||||
# Only supported by VIA
|
||||
if 'VIA_' in extension:
|
||||
instrSet.discard(XMLInstr)
|
||||
@@ -2818,6 +2844,7 @@ def filterInstructions(XMLRoot):
|
||||
if isaSet.startswith('AVX512_VP2INTERSECT') and not cpuid.get_bit(edx7, 8): instrSet.discard(XMLInstr)
|
||||
if extension == 'PCONFIG' and not cpuid.get_bit(edx7, 18): instrSet.discard(XMLInstr)
|
||||
if extension == 'AMX_BF16' and not cpuid.get_bit(edx7, 22): instrSet.discard(XMLInstr)
|
||||
if isaSet.startswith('AVX512_FP16') and not cpuid.get_bit(edx7, 23): instrSet.discard(XMLInstr)
|
||||
if extension == 'AMX_TILE' and not cpuid.get_bit(edx7, 24): instrSet.discard(XMLInstr)
|
||||
if extension == 'AMX_INT8' and not cpuid.get_bit(edx7, 25): instrSet.discard(XMLInstr)
|
||||
if extension == 'AVX_VNNI' and not cpuid.get_bit(eax7_1, 4): instrSet.discard(XMLInstr)
|
||||
|
||||
Reference in New Issue
Block a user