From e6f6dc4a45d3f439029aae50c18de25666780def Mon Sep 17 00:00:00 2001
From: Andreas Abel <abel@cs.uni-saarland.de>
Date: Mon, 15 Nov 2021 18:50:38 +0100
Subject: [PATCH] added TakenAlone option

---
 README.md          |  4 ++--
 common/nanoBench.c | 13 ++++++++++++-
 common/nanoBench.h |  1 +
 3 files changed, 15 insertions(+), 3 deletions(-)

diff --git a/README.md b/README.md
index 03f6629..557248a 100644
--- a/README.md
+++ b/README.md
@@ -177,9 +177,9 @@ We provide provide performance counter configuration files (for counters that ca
 
 The format of the entries in the configuration files is
 
-    EvtSel.UMASK(.CMSK=...)(.AnyT)(.EDG)(.INV)(.CTR=...)(.MSR_3F6H=...)(.MSR_PF=...)(.MSR_RSP0=...)(.MSR_RSP1=...) Name
+    EvtSel.UMASK(.CMSK=...)(.AnyT)(.EDG)(.INV)(.TakenAlone)(.CTR=...)(.MSR_3F6H=...)(.MSR_PF=...)(.MSR_RSP0=...)(.MSR_RSP1=...) Name
 
-You can find details on the meanings of the different parts of the entries in chapters 18 and 19 of [Intel's System Programming Guide](https://software.intel.com/sites/default/files/managed/a4/60/325384-sdm-vol-3abcd.pdf).
+You can find details on the meanings of the different parts of the entries in chapter 18 of [Intel's System Programming Guide](https://www.intel.com/content/www/us/en/develop/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-3a-3b-3c-and-3d-system-programming-guide.html) and at <https://download.01.org/perfmon/readme.txt>.
 
 ## MSR Performance Counter Config Files
 
diff --git a/common/nanoBench.c b/common/nanoBench.c
index 4b1e853..ab87e31 100644
--- a/common/nanoBench.c
+++ b/common/nanoBench.c
@@ -181,6 +181,8 @@ void parse_counter_configs() {
                 pfc_configs[n_pfc_configs].edge = true;
             } else if (!strcmp(ce, "INV")) {
                 pfc_configs[n_pfc_configs].inv = true;
+            } else if (!strcmp(ce, "TakenAlone")) {
+                pfc_configs[n_pfc_configs].taken_alone = true;
             } else if (!strncmp(ce, "CTR=", 4)) {
                 unsigned long counter;
                 nb_strtoul(ce+4, 0, &counter);
@@ -319,15 +321,19 @@ size_t configure_perf_ctrs_programmable(size_t next_pfc_config, int n_counters,
         global_ctrl |= ((uint64_t)7 << 32) | 15;
         write_msr(MSR_IA32_PERF_GLOBAL_CTRL, global_ctrl);
 
+        bool evt_added = false;
         for (int i=0; i<n_counters; i++) {
             // clear
             write_msr(MSR_IA32_PMC0+i, 0);
 
             if (next_pfc_config >= n_pfc_configs) {
-                return next_pfc_config;
+                break;
             }
 
             struct pfc_config config = pfc_configs[next_pfc_config];
+            if (config.taken_alone && evt_added) {
+                break;
+            }
             if ((config.ctr != -1) && (config.ctr != i)) {
                 continue;
             }
@@ -358,6 +364,11 @@ size_t configure_perf_ctrs_programmable(size_t next_pfc_config, int n_counters,
             if (config.msr_rsp1) {
                 write_msr(MSR_OFFCORE_RSP1, config.msr_rsp1);
             }
+
+            evt_added = true;
+            if (config.taken_alone) {
+                break;
+            }
         }
     } else {
         for (int i=0; i<n_counters; i++) {
diff --git a/common/nanoBench.h b/common/nanoBench.h
index c7fe8f7..51708e3 100644
--- a/common/nanoBench.h
+++ b/common/nanoBench.h
@@ -150,6 +150,7 @@ struct pfc_config {
     bool any;
     bool edge;
     bool inv;
+    bool taken_alone;
     unsigned long msr_3f6h;
     unsigned long msr_pf;
     unsigned long msr_rsp0;