23 Commits

Author	SHA1	Message	Date
Andreas Abel	e7c90594e5	improved div_cycles	2021-03-24 20:14:42 +01:00
Andreas Abel	313aa5ee30	python 3	2021-03-13 21:04:52 +01:00
Andreas Abel	d44696f06e	additional LEA variants	2021-03-12 16:14:32 +01:00
Andreas Abel	5df54f1d1d	support for Tiger Lake	2021-03-09 22:31:05 +01:00
Andreas Abel	4971d6c23a	added -df option	2021-03-03 15:47:23 +01:00
Andreas Abel	1d4f3a458a	immzero variants	2021-01-23 16:13:20 +01:00
Andreas Abel	d0f2ba9cc9	padding	2021-01-13 16:07:56 +01:00
Andreas Abel	9ce44e1079	high8 registers	2021-01-04 20:51:23 +01:00
Andreas Abel	a3e586dc12	new extensions	2020-12-04 20:08:22 +01:00
Andreas Abel	1765470b65	complex decoders	2020-11-17 16:12:18 +01:00
Andreas Abel	b86665c1c2	complex decoder	2020-11-16 23:30:27 +01:00
Bartosz Taudul	91cb312015	Add missing checks for AVX512VL. ... There is one variant of VPCLMULQDQ which requires AVX512F instead. Couldn't be bothered to find which one it is.	2020-11-15 17:26:53 +01:00
Bartosz Taudul	210e09b7ab	Add ZEN3 to cpuBench.py.	2020-11-12 23:41:35 +01:00
Andreas Abel	bf0906750b	support for Cascade Lake	2020-10-27 21:48:46 +01:00
Andreas Abel	c3879089b4	minor changes	2020-08-07 15:37:30 +02:00
Andreas Abel	b78a1d3b38	minor changes	2020-08-05 20:18:46 +02:00
Andreas Abel	52231f9a36	macro fusion	2020-08-03 19:54:11 +02:00
Andreas Abel	8f7401178e	support for indexed addressing modes	2020-07-31 15:33:40 +02:00
Andreas Abel	47101197a9	partial reg latencies	2020-05-11 16:11:12 +02:00
Andreas Abel	f9d352cb54	LEA latencies	2020-05-10 21:44:47 +02:00
Andreas Abel	cc66b35dec	movzx same reg	2020-05-08 00:00:23 +02:00
Andreas Abel	be71cd8bdf	x64_lib	2020-05-06 00:15:27 +02:00
Andreas Abel	b7315a4dfb	benchmarks	2020-03-19 21:54:32 +01:00