# Performance monitoring events for processors based on Skylake, Kaby Lake and Coffee Lake microarchitectures.
# Applies to processors with DisplayFamily_DisplayModel of 06_4EH and 06_5EH, 06_8EH, and 06_9EH.
# See Table 19-5 of Intel's "System Programming Guide" (Jan. 2019)

03.02 LD_BLOCKS.STORE_FORWARD
03.08 LD_BLOCKS.NO_SR
07.01 LD_BLOCKS_PARTIAL.ADDRESS_ALIAS
08.01 DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK
08.0E DTLB_LOAD_MISSES.WALK_COMPLETED
08.10 DTLB_LOAD_MISSES.WALK_PENDING
08.10.CMSK=1 DTLB_LOAD_MISSES.WALK_ACTIVE
08.20 DTLB_LOAD_MISSES.STLB_HIT
0D.01 INT_MISC.RECOVERY_CYCLES
0D.01.AnyT INT_MISC.RECOVERY_CYCLES_ANY
0D.80 INT_MISC.CLEAR_RESTEER_CYCLES
0E.01 UOPS_ISSUED.ANY
0E.01.CMSK=1.INV UOPS_ISSUED.STALL_CYCLES
0E.02 UOPS_ISSUED.VECTOR_WIDTH_MISMATCH
0E.20 UOPS_ISSUED.SLOW_LEA
14.01 ARITH.FPU_DIVIDER_ACTIVE
24.21 L2_RQSTS.DEMAND_DATA_RD_MISS
24.22 L2_RQSTS.RFO_MISS
24.24 L2_RQSTS.CODE_RD_MISS
24.27 L2_RQSTS.ALL_DEMAND_MISS
24.38 L2_RQSTS.PF_MISS
24.3F L2_RQSTS.MISS
24.41 L2_RQSTS.DEMAND_DATA_RD_HIT
24.42 L2_RQSTS.RFO_HIT
24.44 L2_RQSTS.CODE_RD_HIT
24.D8 L2_RQSTS.PF_HIT
24.E1 L2_RQSTS.ALL_DEMAND_DATA_RD
24.E2 L2_RQSTS.ALL_RFO
24.E4 L2_RQSTS.ALL_CODE_RD
24.E7 L2_RQSTS.ALL_DEMAND_REFERENCES
24.F8 L2_RQSTS.ALL_PF
24.EF L2_RQSTS.REFERENCES
2E.4F LONGEST_LAT_CACHE.REFERENCE
2E.41 LONGEST_LAT_CACHE.MISS
3C.00 CPU_CLK_UNHALTED.THREAD_P
3C.00.AnyT CPU_CLK_UNHALTED.THREAD_P_ANY
3C.01 CPU_CLK_THREAD_UNHALTED.REF_XCLK
3C.01.AnyT CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY
3C.02 CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE
48.01 L1D_PEND_MISS.PENDING
48.01.CMSK=1 L1D_PEND_MISS.PENDING_CYCLES
48.01.CMSK=1.AnyT L1D_PEND_MISS.PENDING_CYCLES_ANY
48.02 L1D_PEND_MISS.FB_FULL
49.01 DTLB_STORE_MISSES.MISS_CAUSES_A_WALK
49.0E DTLB_STORE_MISSES.WALK_COMPLETED
49.10 DTLB_STORE_MISSES.WALK_PENDING
49.10.CMSK=1 DTLB_STORE_MISSES.WALK_ACTIVE
49.20 DTLB_STORE_MISSES.STLB_HIT
4C.01 LOAD_HIT_PRE.HW_PF
4F.10 EPT.WALK_PENDING
51.01 L1D.REPLACEMENT
5E.01 RS_EVENTS.EMPTY_CYCLES
5E.01.CMSK=1.INV RS_EVENTS.EMPTY_END
60.01 OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD
60.01.CMSK=1 OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD
60.01.CMSK=6 OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_GE_6
60.02 OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD
60.02.CMSK=1 OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_CODE_RD
60.04 OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO
60.04.CMSK=1 OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO
60.08 OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD
60.08.CMSK=1 OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD
60.10 OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD
60.10.CMSK=1 OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_L3_MISS_DEMAND_DATA_RD
60.10.CMSK=6 OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD_GE_6
63.02 LOCK_CYCLES.CACHE_LOCK_DURATION
79.04 IDQ.MITE_UOPS
79.04.CMSK=1 IDQ.MITE_CYCLES
79.08 IDQ.DSB_UOPS
79.08.CMSK=1 IDQ.DSB_CYCLES
79.10 IDQ.MS_DSB_UOPS
79.18.CMSK=1 IDQ.ALL_DSB_CYCLES_ANY_UOPS
79.18.CMSK=4 IDQ.ALL_DSB_CYCLES_4_UOPS
79.20 IDQ.MS_MITE_UOPS
79.24.CMSK=1 IDQ.ALL_MITE_CYCLES_ANY_UOPS
79.24.CMSK=4 IDQ.ALL_MITE_CYCLES_4_UOPS
79.30 IDQ.MS_UOPS
79.30.EDG IDQ.MS_SWITCHES
79.30.CMSK=1 IDQ.MS_CYCLES
80.04 ICACHE_16B.IFDATA_STALL
80.04 ICACHE_64B.IFDATA_STALL
83.01 ICACHE_64B.IFTAG_HIT
83.02 ICACHE_64B.IFTAG_MISS
85.01 ITLB_MISSES.MISS_CAUSES_A_WALK
85.0E ITLB_MISSES.WALK_COMPLETED
85.10 ITLB_MISSES.WALK_PENDING
85.20 ITLB_MISSES.STLB_HIT
87.01 ILD_STALL.LCP
9C.01 IDQ_UOPS_NOT_DELIVERED.CORE
9C.01.CMSK=4 IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOP_DELIV.CORE
9C.01.CMSK=3 IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE
9C.01.CMSK=2 IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE
9C.01.CMSK=1 IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE
9C.01.INV IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK
A1.01 UOPS_DISPATCHED_PORT.PORT_0
A1.02 UOPS_DISPATCHED_PORT.PORT_1
A1.04 UOPS_DISPATCHED_PORT.PORT_2
A1.08 UOPS_DISPATCHED_PORT.PORT_3
A1.10 UOPS_DISPATCHED_PORT.PORT_4
A1.20 UOPS_DISPATCHED_PORT.PORT_5
A1.40 UOPS_DISPATCHED_PORT.PORT_6
A1.80 UOPS_DISPATCHED_PORT.PORT_7
A2.01 RESOURCE_STALLS.ANY
A2.08 RESOURCE_STALLS.SB
A3.01.CMSK=1 CYCLE_ACTIVITY.CYCLES_L2_MISS
A3.02.CMSK=2 CYCLE_ACTIVITY.CYCLES_L3_MISS
A3.04.CMSK=4 CYCLE_ACTIVITY.STALLS_TOTAL
A3.05.CMSK=5 CYCLE_ACTIVITY.STALLS_L2_MISS
A3.06.CMSK=6 CYCLE_ACTIVITY.STALLS_L3_MISS
A3.08.CMSK=8 CYCLE_ACTIVITY.CYCLES_L1D_MISS
A3.0C.CMSK=12 CYCLE_ACTIVITY.STALLS_L1D_MISS
A3.10.CMSK=16 CYCLE_ACTIVITY.CYCLES_MEM_ANY
A3.14.CMSK=20 CYCLE_ACTIVITY.STALLS_MEM_ANY
A6.01 EXE_ACTIVITY.EXE_BOUND_0_PORTS
A6.02 EXE_ACTIVITY.1_PORTS_UTIL
A6.04 EXE_ACTIVITY.2_PORTS_UTIL
A6.08 EXE_ACTIVITY.3_PORTS_UTIL
A6.10 EXE_ACTIVITY.4_PORTS_UTIL
A6.40 EXE_ACTIVITY.BOUND_ON_STORES
A8.01 LSD.UOPS
A8.01.CMSK=1 LSD.CYCLES_ACTIVE
A8.01.CMSK=4 LSD.CYCLES_4_UOPS
AB.02 DSB2MITE_SWITCHES.PENALTY_CYCLES
AE.01 ITLB.ITLB_FLUSH
B0.01 OFFCORE_REQUESTS.DEMAND_DATA_RD
B0.02 OFFCORE_REQUESTS.DEMAND_CODE_RD
B0.04 OFFCORE_REQUESTS.DEMAND_RFO
B0.08 OFFCORE_REQUESTS.ALL_DATA_RD
B0.10 OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD
B0.80 OFFCORE_REQUESTS.ALL_REQUESTS
B1.01 UOPS_EXECUTED.THREAD
B1.01.CMSK=1.INV UOPS_EXECUTED.STALL_CYCLES
B1.01.CMSK=1 UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC
B1.01.CMSK=2 UOPS_EXECUTED.CYCLES_GE_2_UOP_EXEC
B1.01.CMSK=3 UOPS_EXECUTED.CYCLES_GE_3_UOP_EXEC
B1.01.CMSK=4 UOPS_EXECUTED.CYCLES_GE_4_UOP_EXEC
B1.02 UOPS_EXECUTED.CORE
B1.02.CMSK=1 UOPS_EXECUTED.CORE_CYCLES_GE_1
B1.02.CMSK=2 UOPS_EXECUTED.CORE_CYCLES_GE_2
B1.02.CMSK=3 UOPS_EXECUTED.CORE_CYCLES_GE_3
B1.02.CMSK=4 UOPS_EXECUTED.CORE_CYCLES_GE_4
B1.02.CMSK=1.INV UOPS_EXECUTED.CORE_CYCLES_NONE
B1.10 UOPS_EXECUTED.X87
B2.01 OFF_CORE_REQUEST_BUFFER.SQ_FULL
B7.01.CTR=0.MSR_RSP0=0x10001 OFF_CORE_RESPONSE_0.DMND_DATA_RD
B7.01.CTR=0.MSR_RSP0=0x10002 OFF_CORE_RESPONSE_0.DMND_RFO
B7.01.CTR=0.MSR_RSP0=0x10004 OFF_CORE_RESPONSE_0.DMND_IFETCH
B7.01.CTR=0.MSR_RSP0=0x10008 OFF_CORE_RESPONSE_0.WB
B7.01.CTR=0.MSR_RSP0=0x10010 OFF_CORE_RESPONSE_0.PF_DATA_RD
B7.01.CTR=0.MSR_RSP0=0x10020 OFF_CORE_RESPONSE_0.PF_RFO
B7.01.CTR=0.MSR_RSP0=0x10040 OFF_CORE_RESPONSE_0.PF_IFETCH
B7.01.CTR=0.MSR_RSP0=0x10080 OFF_CORE_RESPONSE_0.PF_LLC_DATA_RD
B7.01.CTR=0.MSR_RSP0=0x10100 OFF_CORE_RESPONSE_0.PF_LLC_RFO
B7.01.CTR=0.MSR_RSP0=0x10200 OFF_CORE_RESPONSE_0.PF_LLC_IFETCH
B7.01.CTR=0.MSR_RSP0=0x10400 OFF_CORE_RESPONSE_0.BUS_LOCKS
B7.01.CTR=0.MSR_RSP0=0x10800 OFF_CORE_RESPONSE_0.STRM_ST
B7.01.CTR=0.MSR_RSP0=0x18000 OFF_CORE_RESPONSE_0.OTHER
BB.01.CTR=1.MSR_RSP1=0x10001 OFF_CORE_RESPONSE_1.DMND_DATA_RD
BB.01.CTR=1.MSR_RSP1=0x10002 OFF_CORE_RESPONSE_1.DMND_RFO
BB.01.CTR=1.MSR_RSP1=0x10004 OFF_CORE_RESPONSE_1.DMND_IFETCH
BB.01.CTR=1.MSR_RSP1=0x10008 OFF_CORE_RESPONSE_1.WB
BB.01.CTR=1.MSR_RSP1=0x10010 OFF_CORE_RESPONSE_1.PF_DATA_RD
BB.01.CTR=1.MSR_RSP1=0x10020 OFF_CORE_RESPONSE_1.PF_RFO
BB.01.CTR=1.MSR_RSP1=0x10040 OFF_CORE_RESPONSE_1.PF_IFETCH
BB.01.CTR=1.MSR_RSP1=0x10080 OFF_CORE_RESPONSE_1.PF_LLC_DATA_RD
BB.01.CTR=1.MSR_RSP1=0x10100 OFF_CORE_RESPONSE_1.PF_LLC_RFO
BB.01.CTR=1.MSR_RSP1=0x10200 OFF_CORE_RESPONSE_1.PF_LLC_IFETCH
BB.01.CTR=1.MSR_RSP1=0x10400 OFF_CORE_RESPONSE_1.BUS_LOCKS
BB.01.CTR=1.MSR_RSP1=0x10800 OFF_CORE_RESPONSE_1.STRM_ST
BB.01.CTR=1.MSR_RSP1=0x18000 OFF_CORE_RESPONSE_1.OTHER
BD.01 TLB_FLUSH.DTLB_THREAD
BD.01 TLB_FLUSH.STLB_ANY
C0.00 INST_RETIRED.ANY_P
C0.01.CTR=1 INST_RETIRED.PREC_DIST
C0.01.CMSK=10 INST_RETIRED.TOTAL_CYCLES
C1.3F OTHER_ASSISTS.ANY
C2.01.CMSK=1.INV UOPS_RETIRED.STALL_CYCLES
C2.01.CMSK=10.INV UOPS_RETIRED.TOTAL_CYCLES
C2.02 UOPS_RETIRED.RETIRE_SLOTS
C3.01.CMSK=1.EDG MACHINE_CLEARS.COUNT
C3.02 MACHINE_CLEARS.MEMORY_ORDERING
C3.04 MACHINE_CLEARS.SMC
C4.00 BR_INST_RETIRED.ALL_BRANCHES
C4.01 BR_INST_RETIRED.CONDITIONAL
C4.02 BR_INST_RETIRED.NEAR_CALL
C4.04 BR_INST_RETIRED.ALL_BRANCHES
C4.08 BR_INST_RETIRED.NEAR_RETURN
C4.10 BR_INST_RETIRED.NOT_TAKEN
C4.20 BR_INST_RETIRED.NEAR_TAKEN
C4.40 BR_INST_RETIRED.FAR_BRANCH
C5.00 BR_MISP_RETIRED.ALL_BRANCHES
C5.01 BR_MISP_RETIRED.CONDITIONAL
C5.04 BR_MISP_RETIRED.ALL_BRANCHES
C5.20 BR_MISP_RETIRED.NEAR_TAKEN
C6.01.CTR=0.MSR_PF=0x11 FRONTEND_RETIRED.DSB_MISS
C6.01.CTR=0.MSR_PF=0x12 FRONTEND_RETIRED.L1I_MISS
C6.01.CTR=0.MSR_PF=0x13 FRONTEND_RETIRED.L2_MISS
C6.01.CTR=0.MSR_PF=0x14 FRONTEND_RETIRED.ITLB_MISS
C6.01.CTR=0.MSR_PF=0x15 FRONTEND_RETIRED.STLB_MISS
C6.01.CTR=0.MSR_PF=0x401016 FRONTEND_RETIRED.LATENCY_GE_16
C6.01.CTR=0.MSR_PF=0x100216 FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1
C6.01.CTR=0.MSR_PF=0x200216 FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_2
C6.01.CTR=0.MSR_PF=0x400216 FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_3
C7.01 FP_ARITH_INST_RETIRED.SCALAR_DOUBLE
C7.02 FP_ARITH_INST_RETIRED.SCALAR_SINGLE
C7.04 FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE
C7.08 FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE
C7.10 FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE
C7.20 FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE
CA.1E.CMSK=1 FP_ASSIST.ANY
CB.01 HW_INTERRUPTS.RECEIVED
CD.01.MSR_3F6H=10 MEM_TRANS_RETIRED.LOAD_LATENCY
D0.11 MEM_INST_RETIRED.STLB_MISS_LOADS
D0.12 MEM_INST_RETIRED.STLB_MISS_STORES
D0.21 MEM_INST_RETIRED.LOCK_LOADS
D0.41 MEM_INST_RETIRED.SPLIT_LOADS
D0.42 MEM_INST_RETIRED.SPLIT_STORES
D0.81 MEM_INST_RETIRED.ALL_LOADS
D0.82 MEM_INST_RETIRED.ALL_STORES
D1.01 MEM_LOAD_RETIRED.L1_HIT
D1.02 MEM_LOAD_RETIRED.L2_HIT
D1.04 MEM_LOAD_RETIRED.L3_HIT
D1.08 MEM_LOAD_RETIRED.L1_MISS
D1.10 MEM_LOAD_RETIRED.L2_MISS
D1.20 MEM_LOAD_RETIRED.L3_MISS
D1.40 MEM_LOAD_RETIRED.FB_HIT
D2.01 MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS
D2.02 MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT
D2.04 MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM
D2.08 MEM_LOAD_L3_HIT_RETIRED.XSNP_NONE
E6.01 BACLEARS.ANY
F0.40 L2_TRANS.L2_WB
F1.07 L2_LINES_IN.ALL