# Based on https://download.01.org/perfmon/TGL/tigerlake_core_v1.05.json
# Applies to processors with family-model in {6-8C, 6-8D}

3C.00 CORE_CYCLES
C0.00 INST_RETIRED
79.04 IDQ.MITE_UOPS
79.08 IDQ.DSB_UOPS
79.30 IDQ.MS_UOPS
A8.01 LSD.UOPS
0E.01 UOPS_ISSUED
B1.01 UOPS_EXECUTED
C2.02 UOPS_RETIRED.SLOTS
A1.01 UOPS_DISPATCHED.PORT_0
A1.02 UOPS_DISPATCHED.PORT_1
A1.04 UOPS_DISPATCHED.PORT_2_3
A1.10 UOPS_DISPATCHED.PORT_4_9
A1.20 UOPS_DISPATCHED.PORT_5
A1.40 UOPS_DISPATCHED.PORT_6
A1.80 UOPS_DISPATCHED.PORT_7_8
C4.00 BR_INST_RETIRED.ALL_BRANCHES
C5.00 BR_MISP_RETIRED.ALL_BRANCHES
D1.01 MEM_LOAD_RETIRED.L1_HIT
D1.08 MEM_LOAD_RETIRED.L1_MISS
D1.02 MEM_LOAD_RETIRED.L2_HIT
D1.10 MEM_LOAD_RETIRED.L2_MISS
D1.04 MEM_LOAD_RETIRED.L3_HIT
D1.20 MEM_LOAD_RETIRED.L3_MISS