# Performance monitoring events for processors based on the Ivy Bridge microarchitecture.
# Applies to processors with DisplayFamily_DisplayModel of 06_3AH.
# See Table 19-14 of Intel's "System Programming Guide" (Jan. 2019)

03.02 LD_BLOCKS.STORE_FORWARD
03.08 LD_BLOCKS.NO_SR
05.01 MISALIGN_MEM_REF.LOADS
05.02 MISALIGN_MEM_REF.STORES
07.01 LD_BLOCKS_PARTIAL.ADDRESS_ALIAS
08.81 DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK
08.82 DTLB_LOAD_MISSES.WALK_COMPLETED
08.84 DTLB_LOAD_MISSES.WALK_DURATION
08.88 DTLB_LOAD_MISSES.LARGE_PAGE_WALK_DURATION
0E.01 UOPS_ISSUED.ANY
0E.10 UOPS_ISSUED.FLAGS_MERGE
0E.20 UOPS_ISSUED.SLOW_LEA
0E.40 UOPS_ISSUED.SiNGLE_MUL
10.01 FP_COMP_OPS_EXE.X87
10.10 FP_COMP_OPS_EXE.SSE_FP_PACKED_DOUBLE
10.20 FP_COMP_OPS_EXE.SSE_FP_SCALAR_SINGLE
10.40 FP_COMP_OPS_EXE.SSE_PACKEDSINGLE
10.80 FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE
11.01 SIMD_FP_256.PACKED_SINGLE
11.02 SIMD_FP_256.PACKED_DOUBLE
14.01 ARITH.FPU_DIV_ACTIVE
24.01 L2_RQSTS.DEMAND_DATA_RD_HIT
24.03 L2_RQSTS.ALL_DEMAND_DATA_RD
24.04 L2_RQSTS.RFO_HITS
24.08 L2_RQSTS.RFO_MISS
24.0C L2_RQSTS.ALL_RFO
24.10 L2_RQSTS.CODE_RD_HIT
24.20 L2_RQSTS.CODE_RD_MISS
24.30 L2_RQSTS.ALL_CODE_RD
24.40 L2_RQSTS.PF_HIT
24.80 L2_RQSTS.PF_MISS
24.C0 L2_RQSTS.ALL_PF
27.01 L2_STORE_LOCK_RQSTS.MISS
27.08 L2_STORE_LOCK_RQSTS.HIT_M
27.0F L2_STORE_LOCK_RQSTS.ALL
28.01 L2_L1D_WB_RQSTS.MISS
28.04 L2_L1D_WB_RQSTS.HIT_E
28.08 L2_L1D_WB_RQSTS.HIT_M
28.0F L2_L1D_WB_RQSTS.ALL
2E.4F LONGEST_LAT_CACHE.REFERENCE
2E.41 LONGEST_LAT_CACHE.MISS
3C.00 CPU_CLK_UNHALTED.THREAD_P
3C.01 CPU_CLK_THREAD_UNHALTED.REF_XCLK
48.01.CTR=2 L1D_PEND_MISS.PENDING
49.01 DTLB_STORE_MISSES.MISS_CAUSES_A_WALK
49.02 DTLB_STORE_MISSES.WALK_COMPLETED
49.04 DTLB_STORE_MISSES.WALK_DURATION
49.10 DTLB_STORE_MISSES.STLB_HIT
4C.01 LOAD_HIT_PRE.SW_PF
4C.02 LOAD_HIT_PRE.HW_PF
51.01 L1D.REPLACEMENT
58.04 MOVE_ELIMINATION.INT_NOT_ELIMINATED
58.08 MOVE_ELIMINATION.SIMD_NOT_ELIMINATED
58.01 MOVE_ELIMINATION.INT_ELIMINATED
58.02 MOVE_ELIMINATION.SIMD_ELIMINATED
5C.01 CPL_CYCLES.RING0
5C.02 CPL_CYCLES.RING123
5E.01 RS_EVENTS.EMPTY_CYCLES
5F.04 DTLB_LOAD_MISSES.STLB_HIT
60.01 OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD
60.02 OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD
60.04 OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO
60.08 OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD
63.01 LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION
63.02 LOCK_CYCLES.CACHE_LOCK_DURATION
79.02 IDQ.EMPTY
79.04 IDQ.MITE_UOPS
79.08 IDQ.DSB_UOPS
79.10 IDQ.MS_DSB_UOPS
79.20 IDQ.MS_MITE_UOPS
79.30 IDQ.MS_UOPS
79.18.CMSK=1 IDQ.ALL_DSB_CYCLES_ANY_UOPS
79.18.CMSK=4 IDQ.ALL_DSB_CYCLES_4_UOPS
79.24.CMSK=1 IDQ.ALL_MITE_CYCLES_ANY_UOPS
79.24.CMSK=4 IDQ.ALL_MITE_CYCLES_4_UOPS
79.3C IDQ.MITE_ALL_UOPS
80.04 ICACHE.IFETCH_STALL
80.02 ICACHE.MISSES
85.01 ITLB_MISSES.MISS_CAUSES_A_WALK
85.02 ITLB_MISSES.WALK_COMPLETED
85.04 ITLB_MISSES.WALK_DURATION
85.10 ITLB_MISSES.STLB_HIT
87.01 ILD_STALL.LCP
87.04 ILD_STALL.IQ_FULL
88.01 BR_INST_EXEC.COND
88.02 BR_INST_EXEC.DIRECT_JMP
88.04 BR_INST_EXEC.INDIRECT_JMP_NON_CALL_RET
88.08 BR_INST_EXEC.RETURN_NEAR
88.10 BR_INST_EXEC.DIRECT_NEAR_CALL
88.20 BR_INST_EXEC.INDIRECT_NEAR_CALL
88.40 BR_INST_EXEC.NONTAKEN
88.80 BR_INST_EXEC.TAKEN
88.FF BR_INST_EXEC.ALL_BRANCHES
89.01 BR_MISP_EXEC.COND
89.04 BR_MISP_EXEC.INDIRECT_JMP_NON_CALL_RET
89.08 BR_MISP_EXEC.RETURN_NEAR
89.10 BR_MISP_EXEC.DIRECT_NEAR_CALL
89.20 BR_MISP_EXEC.INDIRECT_NEAR_CALL
89.40 BR_MISP_EXEC.NONTAKEN
89.80 BR_MISP_EXEC.TAKEN
89.FF BR_MISP_EXEC.ALL_BRANCHES
9C.01 IDQ_UOPS_NOT_DELIVERED.CORE
A1.01 UOPS_DISPATCHED_PORT.PORT_0
A1.02 UOPS_DISPATCHED_PORT.PORT_1
A1.0C UOPS_DISPATCHED_PORT.PORT_2
A1.30 UOPS_DISPATCHED_PORT.PORT_3
A1.40 UOPS_DISPATCHED_PORT.PORT_4
A1.80 UOPS_DISPATCHED_PORT.PORT_5
A2.01 RESOURCE_STALLS.ANY
A2.04 RESOURCE_STALLS.RS
A2.08 RESOURCE_STALLS.SB
A2.10 RESOURCE_STALLS.ROB
A3.01 CYCLE_ACTIVITY.CYCLES_L2_PENDING
A3.02 CYCLE_ACTIVITY.CYCLES_LDM_PENDING
A3.04 CYCLE_ACTIVITY.CYCLES_NO_EXECUTE
A3.05 CYCLE_ACTIVITY.STALLS_L2_PENDING
A3.06 CYCLE_ACTIVITY.STALLS_LDM_PENDING
A3.08.CTR=2 CYCLE_ACTIVITY.CYCLES_L1D_PENDING
A3.0C.CTR=2.CMSK=0x0C CYCLE_ACTIVITY.STALLS_L1D_PENDING
A8.01 LSD.UOPS
AB.01 DSB2MITE_SWITCHES.COUNT
AB.02 DSB2MITE_SWITCHES.PENALTY_CYCLES
AC.08 DSB_FILL.EXCEED_DSB_LINES
AE.01 ITLB.ITLB_FLUSH
B0.01 OFFCORE_REQUESTS.DEMAND_DATA_RD
B0.02 OFFCORE_REQUESTS.DEMAND_CODE_RD
B0.04 OFFCORE_REQUESTS.DEMAND_RFO
B0.08 OFFCORE_REQUESTS.ALL_DATA_RD
B1.01 UOPS_EXECUTED.THREAD
B1.02 UOPS_EXECUTED.CORE
B7.01.CTR=0.MSR_RSP0=0x10001 OFF_CORE_RESPONSE_0.DMND_DATA_RD
B7.01.CTR=0.MSR_RSP0=0x10002 OFF_CORE_RESPONSE_0.DMND_RFO
B7.01.CTR=0.MSR_RSP0=0x10004 OFF_CORE_RESPONSE_0.DMND_IFETCH
B7.01.CTR=0.MSR_RSP0=0x10008 OFF_CORE_RESPONSE_0.WB
B7.01.CTR=0.MSR_RSP0=0x10010 OFF_CORE_RESPONSE_0.PF_DATA_RD
B7.01.CTR=0.MSR_RSP0=0x10020 OFF_CORE_RESPONSE_0.PF_RFO
B7.01.CTR=0.MSR_RSP0=0x10040 OFF_CORE_RESPONSE_0.PF_IFETCH
B7.01.CTR=0.MSR_RSP0=0x10080 OFF_CORE_RESPONSE_0.PF_LLC_DATA_RD
B7.01.CTR=0.MSR_RSP0=0x10100 OFF_CORE_RESPONSE_0.PF_LLC_RFO
B7.01.CTR=0.MSR_RSP0=0x10200 OFF_CORE_RESPONSE_0.PF_LLC_IFETCH
B7.01.CTR=0.MSR_RSP0=0x10400 OFF_CORE_RESPONSE_0.BUS_LOCKS
B7.01.CTR=0.MSR_RSP0=0x10800 OFF_CORE_RESPONSE_0.STRM_ST
B7.01.CTR=0.MSR_RSP0=0x18000 OFF_CORE_RESPONSE_0.OTHER
BB.01.CTR=1.MSR_RSP1=0x10001 OFF_CORE_RESPONSE_1.DMND_DATA_RD
BB.01.CTR=1.MSR_RSP1=0x10002 OFF_CORE_RESPONSE_1.DMND_RFO
BB.01.CTR=1.MSR_RSP1=0x10004 OFF_CORE_RESPONSE_1.DMND_IFETCH
BB.01.CTR=1.MSR_RSP1=0x10008 OFF_CORE_RESPONSE_1.WB
BB.01.CTR=1.MSR_RSP1=0x10010 OFF_CORE_RESPONSE_1.PF_DATA_RD
BB.01.CTR=1.MSR_RSP1=0x10020 OFF_CORE_RESPONSE_1.PF_RFO
BB.01.CTR=1.MSR_RSP1=0x10040 OFF_CORE_RESPONSE_1.PF_IFETCH
BB.01.CTR=1.MSR_RSP1=0x10080 OFF_CORE_RESPONSE_1.PF_LLC_DATA_RD
BB.01.CTR=1.MSR_RSP1=0x10100 OFF_CORE_RESPONSE_1.PF_LLC_RFO
BB.01.CTR=1.MSR_RSP1=0x10200 OFF_CORE_RESPONSE_1.PF_LLC_IFETCH
BB.01.CTR=1.MSR_RSP1=0x10400 OFF_CORE_RESPONSE_1.BUS_LOCKS
BB.01.CTR=1.MSR_RSP1=0x10800 OFF_CORE_RESPONSE_1.STRM_ST
BB.01.CTR=1.MSR_RSP1=0x18000 OFF_CORE_RESPONSE_1.OTHER
BD.01 TLB_FLUSH.DTLB_THREAD
BD.20 TLB_FLUSH.STLB_ANY
C0.00 INST_RETIRED.ANY_P
C0.01.CTR=1 INST_RETIRED.PREC_DIST
C1.08 OTHER_ASSISTS.AVX_STORE
C1.10 OTHER_ASSISTS.AVX_TO_SSE
C1.20 OTHER_ASSISTS.SSE_TO_AVX
C1.80 OTHER_ASSISTS.WB
C2.01 UOPS_RETIRED.ALL
C2.02 UOPS_RETIRED.RETIRE_SLOTS
C3.02 MACHINE_CLEARS.MEMORY_ORDERING
C3.04 MACHINE_CLEARS.SMC
C3.20 MACHINE_CLEARS.MASKMOV
C4.00 BR_INST_RETIRED.ALL_BRANCHES
C4.01 BR_INST_RETIRED.CONDITIONAL
C4.02 BR_INST_RETIRED.NEAR_CALL
C4.04 BR_INST_RETIRED.ALL_BRANCHES
C4.08 BR_INST_RETIRED.NEAR_RETURN
C4.10 BR_INST_RETIRED.NOT_TAKEN
C4.20 BR_INST_RETIRED.NEAR_TAKEN
C4.40 BR_INST_RETIRED.FAR_BRANCH
C5.00 BR_MISP_RETIRED.ALL_BRANCHES
C5.01 BR_MISP_RETIRED.CONDITIONAL
C5.04 BR_MISP_RETIRED.ALL_BRANCHES
C5.20 BR_MISP_RETIRED.NEAR_TAKEN
CA.02 FP_ASSIST.X87_OUTPUT
CA.04 FP_ASSIST.X87_INPUT
CA.08 FP_ASSIST.SIMD_OUTPUT
CA.10 FP_ASSIST.SIMD_INPUT
CA.1E FP_ASSIST.ANY
CC.20 ROB_MISC_EVENTS.LBR_INSERTS
CD.01.CTR=3.MSR_3F6H=10 MEM_TRANS_RETIRED.LOAD_LATENCY
CD.02.CTR=3 MEM_TRANS_RETIRED.PRECISE_STORE
D0.11 MEM_UOPS_RETIRED.STLB_MISS_LOADS
D0.12 MEM_UOPS_RETIRED.STLB_MISS_STORES
D0.21 MEM_UOPS_RETIRED.LOCK_LOADS
D0.41 MEM_UOPS_RETIRED.SPLIT_LOADS
D0.42 MEM_UOPS_RETIRED.SPLIT_STORES
D0.81 MEM_UOPS_RETIRED.ALL_LOADS
D0.82 MEM_UOPS_RETIRED.ALL_STORES
D1.01 MEM_LOAD_UOPS_RETIRED.L1_HIT
D1.02 MEM_LOAD_UOPS_RETIRED.L2_HIT
D1.04 MEM_LOAD_UOPS_RETIRED.LLC_HIT
D1.08 MEM_LOAD_UOPS_RETIRED.L1_MISS
D1.10 MEM_LOAD_UOPS_RETIRED.L2_MISS
D1.20 MEM_LOAD_UOPS_RETIRED.LLC_MISS
D1.40 MEM_LOAD_UOPS_RETIRED.HIT_LFB
D2.01 MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS
D2.02 MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT
D2.04 MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM
D2.08 MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE
D3.01 MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM
E6.1F BACLEARS.ANY
F0.01 L2_TRANS.DEMAND_DATA_RD
F0.02 L2_TRANS.RFO
F0.04 L2_TRANS.CODE_RD
F0.08 L2_TRANS.ALL_PF
F0.10 L2_TRANS.L1D_WB
F0.20 L2_TRANS.L2_FILL
F0.40 L2_TRANS.L2_WB
F0.80 L2_TRANS.ALL_REQUESTS
F1.01 L2_LINES_IN.I
F1.02 L2_LINES_IN.S
F1.04 L2_LINES_IN.E
F1.07 L2_LINES_IN.ALL
F2.01 L2_LINES_OUT.DEMAND_CLEAN
F2.02 L2_LINES_OUT.DEMAND_DIRTY
F2.04 L2_LINES_OUT.PF_CLEAN
F2.08 L2_LINES_OUT.PF_DIRTY
F2.0A L2_LINES_OUT.DIRTY_ALL