nanoBench/configs/cfg_Goldmont_all_offcore.txt

# Based on https://download.01.org/perfmon/GLM/goldmont_core_v13.json
# Applies to processors with family-model in {6-5C, 6-5F}

# Counts bus lock and split lock requests that have any transaction responses from the uncore subsystem.
B7.01.MSR_RSP0=0x0000010400.TakenAlone OFFCORE_RESPONSE.BUS_LOCKS.ANY_RESPONSE

# Counts requests to the uncore subsystem that have any transaction responses from the uncore subsystem.
B7.01.MSR_RSP0=0x0000018000.TakenAlone OFFCORE_RESPONSE.ANY_REQUEST.ANY_RESPONSE

# Counts demand cacheable data reads of full cache lines that hit the L2 cache.
B7.01.MSR_RSP0=0x0000040001.TakenAlone OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_HIT

# Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that hit the L2 cache.
B7.01.MSR_RSP0=0x0000040002.TakenAlone OFFCORE_RESPONSE.DEMAND_RFO.L2_HIT

# Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that hit the L2 cache.
B7.01.MSR_RSP0=0x0000040004.TakenAlone OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_HIT

# Counts the number of writeback transactions caused by L1 or L2 cache evictions that hit the L2 cache.
B7.01.MSR_RSP0=0x0000040008.TakenAlone OFFCORE_RESPONSE.COREWB.L2_HIT

# Counts data cacheline reads generated by hardware L2 cache prefetcher that hit the L2 cache.
B7.01.MSR_RSP0=0x0000040010.TakenAlone OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_HIT

# Counts reads for ownership (RFO) requests generated by L2 prefetcher that hit the L2 cache.
B7.01.MSR_RSP0=0x0000040020.TakenAlone OFFCORE_RESPONSE.PF_L2_RFO.L2_HIT

# Counts reads for ownership (RFO) requests (demand & prefetch) that hit the L2 cache.
B7.01.MSR_RSP0=0x0000040022.TakenAlone OFFCORE_RESPONSE.ANY_RFO.L2_HIT

# Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes that hit the L2 cache.
B7.01.MSR_RSP0=0x0000040800.TakenAlone OFFCORE_RESPONSE.FULL_STREAMING_STORES.L2_HIT

# Counts data cache lines requests by software prefetch instructions that hit the L2 cache.
B7.01.MSR_RSP0=0x0000041000.TakenAlone OFFCORE_RESPONSE.SW_PREFETCH.L2_HIT

# Counts data cache line reads generated by hardware L1 data cache prefetcher that hit the L2 cache.
B7.01.MSR_RSP0=0x0000042000.TakenAlone OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_HIT

# Counts data reads generated by L1 or L2 prefetchers that hit the L2 cache.
B7.01.MSR_RSP0=0x0000043010.TakenAlone OFFCORE_RESPONSE.ANY_PF_DATA_RD.L2_HIT

# Counts data reads (demand & prefetch) that hit the L2 cache.
B7.01.MSR_RSP0=0x0000043091.TakenAlone OFFCORE_RESPONSE.ANY_DATA_RD.L2_HIT

# Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that hit the L2 cache.
B7.01.MSR_RSP0=0x00000432b7.TakenAlone OFFCORE_RESPONSE.ANY_READ.L2_HIT

# Counts partial cache line data writes to uncacheable write combining (USWC) memory region  that hit the L2 cache.
B7.01.MSR_RSP0=0x0000044000.TakenAlone OFFCORE_RESPONSE.PARTIAL_STREAMING_STORES.L2_HIT

# Counts any data writes to uncacheable write combining (USWC) memory region  that hit the L2 cache.
B7.01.MSR_RSP0=0x0000044800.TakenAlone OFFCORE_RESPONSE.STREAMING_STORES.L2_HIT

# Counts requests to the uncore subsystem that hit the L2 cache.
B7.01.MSR_RSP0=0x0000048000.TakenAlone OFFCORE_RESPONSE.ANY_REQUEST.L2_HIT

# Counts demand cacheable data reads of full cache lines that true miss for the L2 cache with a snoop miss in the other processor module. 
B7.01.MSR_RSP0=0x0200000001.TakenAlone OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED

# Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that true miss for the L2 cache with a snoop miss in the other processor module. 
B7.01.MSR_RSP0=0x0200000002.TakenAlone OFFCORE_RESPONSE.DEMAND_RFO.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED

# Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that true miss for the L2 cache with a snoop miss in the other processor module. 
B7.01.MSR_RSP0=0x0200000004.TakenAlone OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED

# Counts the number of writeback transactions caused by L1 or L2 cache evictions that true miss for the L2 cache with a snoop miss in the other processor module. 
B7.01.MSR_RSP0=0x0200000008.TakenAlone OFFCORE_RESPONSE.COREWB.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED

# Counts data cacheline reads generated by hardware L2 cache prefetcher that true miss for the L2 cache with a snoop miss in the other processor module. 
B7.01.MSR_RSP0=0x0200000010.TakenAlone OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED

# Counts reads for ownership (RFO) requests generated by L2 prefetcher that true miss for the L2 cache with a snoop miss in the other processor module. 
B7.01.MSR_RSP0=0x0200000020.TakenAlone OFFCORE_RESPONSE.PF_L2_RFO.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED

# Counts reads for ownership (RFO) requests (demand & prefetch) that true miss for the L2 cache with a snoop miss in the other processor module. 
B7.01.MSR_RSP0=0x0200000022.TakenAlone OFFCORE_RESPONSE.ANY_RFO.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED

# Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes that true miss for the L2 cache with a snoop miss in the other processor module. 
B7.01.MSR_RSP0=0x0200000800.TakenAlone OFFCORE_RESPONSE.FULL_STREAMING_STORES.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED

# Counts data cache lines requests by software prefetch instructions that true miss for the L2 cache with a snoop miss in the other processor module. 
B7.01.MSR_RSP0=0x0200001000.TakenAlone OFFCORE_RESPONSE.SW_PREFETCH.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED

# Counts data cache line reads generated by hardware L1 data cache prefetcher that true miss for the L2 cache with a snoop miss in the other processor module. 
B7.01.MSR_RSP0=0x0200002000.TakenAlone OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED

# Counts data reads generated by L1 or L2 prefetchers that true miss for the L2 cache with a snoop miss in the other processor module. 
B7.01.MSR_RSP0=0x0200003010.TakenAlone OFFCORE_RESPONSE.ANY_PF_DATA_RD.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED

# Counts data reads (demand & prefetch) that true miss for the L2 cache with a snoop miss in the other processor module. 
B7.01.MSR_RSP0=0x0200003091.TakenAlone OFFCORE_RESPONSE.ANY_DATA_RD.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED

# Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that true miss for the L2 cache with a snoop miss in the other processor module. 
B7.01.MSR_RSP0=0x02000032b7.TakenAlone OFFCORE_RESPONSE.ANY_READ.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED

# Counts partial cache line data writes to uncacheable write combining (USWC) memory region  that true miss for the L2 cache with a snoop miss in the other processor module. 
B7.01.MSR_RSP0=0x0200004000.TakenAlone OFFCORE_RESPONSE.PARTIAL_STREAMING_STORES.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED

# Counts requests to the uncore subsystem that true miss for the L2 cache with a snoop miss in the other processor module. 
B7.01.MSR_RSP0=0x0200008000.TakenAlone OFFCORE_RESPONSE.ANY_REQUEST.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED

# Counts demand cacheable data reads of full cache lines that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required.
B7.01.MSR_RSP0=0x0400000001.TakenAlone OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_MISS.HIT_OTHER_CORE_NO_FWD

# Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required.
B7.01.MSR_RSP0=0x0400000002.TakenAlone OFFCORE_RESPONSE.DEMAND_RFO.L2_MISS.HIT_OTHER_CORE_NO_FWD

# Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required.
B7.01.MSR_RSP0=0x0400000004.TakenAlone OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_MISS.HIT_OTHER_CORE_NO_FWD

# Counts the number of writeback transactions caused by L1 or L2 cache evictions that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required.
B7.01.MSR_RSP0=0x0400000008.TakenAlone OFFCORE_RESPONSE.COREWB.L2_MISS.HIT_OTHER_CORE_NO_FWD

# Counts data cacheline reads generated by hardware L2 cache prefetcher that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required.
B7.01.MSR_RSP0=0x0400000010.TakenAlone OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_MISS.HIT_OTHER_CORE_NO_FWD

# Counts reads for ownership (RFO) requests generated by L2 prefetcher that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required.
B7.01.MSR_RSP0=0x0400000020.TakenAlone OFFCORE_RESPONSE.PF_L2_RFO.L2_MISS.HIT_OTHER_CORE_NO_FWD

# Counts reads for ownership (RFO) requests (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required.
B7.01.MSR_RSP0=0x0400000022.TakenAlone OFFCORE_RESPONSE.ANY_RFO.L2_MISS.HIT_OTHER_CORE_NO_FWD

# Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required.
B7.01.MSR_RSP0=0x0400000800.TakenAlone OFFCORE_RESPONSE.FULL_STREAMING_STORES.L2_MISS.HIT_OTHER_CORE_NO_FWD

# Counts data cache lines requests by software prefetch instructions that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required.
B7.01.MSR_RSP0=0x0400001000.TakenAlone OFFCORE_RESPONSE.SW_PREFETCH.L2_MISS.HIT_OTHER_CORE_NO_FWD

# Counts data cache line reads generated by hardware L1 data cache prefetcher that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required.
B7.01.MSR_RSP0=0x0400002000.TakenAlone OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_MISS.HIT_OTHER_CORE_NO_FWD

# Counts data reads generated by L1 or L2 prefetchers that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required.
B7.01.MSR_RSP0=0x0400003010.TakenAlone OFFCORE_RESPONSE.ANY_PF_DATA_RD.L2_MISS.HIT_OTHER_CORE_NO_FWD

# Counts data reads (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required.
B7.01.MSR_RSP0=0x0400003091.TakenAlone OFFCORE_RESPONSE.ANY_DATA_RD.L2_MISS.HIT_OTHER_CORE_NO_FWD

# Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required.
B7.01.MSR_RSP0=0x04000032b7.TakenAlone OFFCORE_RESPONSE.ANY_READ.L2_MISS.HIT_OTHER_CORE_NO_FWD

# Counts partial cache line data writes to uncacheable write combining (USWC) memory region  that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required.
B7.01.MSR_RSP0=0x0400004000.TakenAlone OFFCORE_RESPONSE.PARTIAL_STREAMING_STORES.L2_MISS.HIT_OTHER_CORE_NO_FWD

# Counts requests to the uncore subsystem that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required.
B7.01.MSR_RSP0=0x0400008000.TakenAlone OFFCORE_RESPONSE.ANY_REQUEST.L2_MISS.HIT_OTHER_CORE_NO_FWD

# Counts demand cacheable data reads of full cache lines that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.
B7.01.MSR_RSP0=0x1000000001.TakenAlone OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_MISS.HITM_OTHER_CORE

# Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.
B7.01.MSR_RSP0=0x1000000002.TakenAlone OFFCORE_RESPONSE.DEMAND_RFO.L2_MISS.HITM_OTHER_CORE

# Counts the number of writeback transactions caused by L1 or L2 cache evictions that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.
B7.01.MSR_RSP0=0x1000000008.TakenAlone OFFCORE_RESPONSE.COREWB.L2_MISS.HITM_OTHER_CORE

# Counts data cacheline reads generated by hardware L2 cache prefetcher that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.
B7.01.MSR_RSP0=0x1000000010.TakenAlone OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_MISS.HITM_OTHER_CORE

# Counts reads for ownership (RFO) requests generated by L2 prefetcher that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.
B7.01.MSR_RSP0=0x1000000020.TakenAlone OFFCORE_RESPONSE.PF_L2_RFO.L2_MISS.HITM_OTHER_CORE

# Counts reads for ownership (RFO) requests (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.
B7.01.MSR_RSP0=0x1000000022.TakenAlone OFFCORE_RESPONSE.ANY_RFO.L2_MISS.HITM_OTHER_CORE

# Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.
B7.01.MSR_RSP0=0x1000000800.TakenAlone OFFCORE_RESPONSE.FULL_STREAMING_STORES.L2_MISS.HITM_OTHER_CORE

# Counts data cache lines requests by software prefetch instructions that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.
B7.01.MSR_RSP0=0x1000001000.TakenAlone OFFCORE_RESPONSE.SW_PREFETCH.L2_MISS.HITM_OTHER_CORE

# Counts data cache line reads generated by hardware L1 data cache prefetcher that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.
B7.01.MSR_RSP0=0x1000002000.TakenAlone OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_MISS.HITM_OTHER_CORE

# Counts data reads generated by L1 or L2 prefetchers that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.
B7.01.MSR_RSP0=0x1000003010.TakenAlone OFFCORE_RESPONSE.ANY_PF_DATA_RD.L2_MISS.HITM_OTHER_CORE

# Counts data reads (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.
B7.01.MSR_RSP0=0x1000003091.TakenAlone OFFCORE_RESPONSE.ANY_DATA_RD.L2_MISS.HITM_OTHER_CORE

# Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.
B7.01.MSR_RSP0=0x10000032b7.TakenAlone OFFCORE_RESPONSE.ANY_READ.L2_MISS.HITM_OTHER_CORE

# Counts partial cache line data writes to uncacheable write combining (USWC) memory region  that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.
B7.01.MSR_RSP0=0x1000004000.TakenAlone OFFCORE_RESPONSE.PARTIAL_STREAMING_STORES.L2_MISS.HITM_OTHER_CORE

# Counts requests to the uncore subsystem that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.
B7.01.MSR_RSP0=0x1000008000.TakenAlone OFFCORE_RESPONSE.ANY_REQUEST.L2_MISS.HITM_OTHER_CORE

# Counts demand cacheable data reads of full cache lines that miss the L2 cache.
B7.01.MSR_RSP0=0x3600000001.TakenAlone OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_MISS.ANY

# Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that miss the L2 cache.
B7.01.MSR_RSP0=0x3600000002.TakenAlone OFFCORE_RESPONSE.DEMAND_RFO.L2_MISS.ANY

# Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that miss the L2 cache.
B7.01.MSR_RSP0=0x3600000004.TakenAlone OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_MISS.ANY

# Counts the number of writeback transactions caused by L1 or L2 cache evictions that miss the L2 cache.
B7.01.MSR_RSP0=0x3600000008.TakenAlone OFFCORE_RESPONSE.COREWB.L2_MISS.ANY

# Counts data cacheline reads generated by hardware L2 cache prefetcher that miss the L2 cache.
B7.01.MSR_RSP0=0x3600000010.TakenAlone OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_MISS.ANY

# Counts reads for ownership (RFO) requests generated by L2 prefetcher that miss the L2 cache.
B7.01.MSR_RSP0=0x3600000020.TakenAlone OFFCORE_RESPONSE.PF_L2_RFO.L2_MISS.ANY

# Counts reads for ownership (RFO) requests (demand & prefetch) that miss the L2 cache.
B7.01.MSR_RSP0=0x3600000022.TakenAlone OFFCORE_RESPONSE.ANY_RFO.L2_MISS.ANY

# Counts demand data partial reads, including data in uncacheable (UC) or uncacheable write combining (USWC) memory types that miss the L2 cache.
B7.01.MSR_RSP0=0x3600000080.TakenAlone OFFCORE_RESPONSE.PARTIAL_READS.L2_MISS.ANY

# Counts the number of demand write requests (RFO) generated by a write to partial data cache line, including the writes to uncacheable (UC) and write through (WT), and write protected (WP) types of memory that miss the L2 cache.
B7.01.MSR_RSP0=0x3600000100.TakenAlone OFFCORE_RESPONSE.PARTIAL_WRITES.L2_MISS.ANY

# Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes that miss the L2 cache.
B7.01.MSR_RSP0=0x3600000800.TakenAlone OFFCORE_RESPONSE.FULL_STREAMING_STORES.L2_MISS.ANY

# Counts data cache lines requests by software prefetch instructions that miss the L2 cache.
B7.01.MSR_RSP0=0x3600001000.TakenAlone OFFCORE_RESPONSE.SW_PREFETCH.L2_MISS.ANY

# Counts data cache line reads generated by hardware L1 data cache prefetcher that miss the L2 cache.
B7.01.MSR_RSP0=0x3600002000.TakenAlone OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_MISS.ANY

# Counts data reads generated by L1 or L2 prefetchers that miss the L2 cache.
B7.01.MSR_RSP0=0x3600003010.TakenAlone OFFCORE_RESPONSE.ANY_PF_DATA_RD.L2_MISS.ANY

# Counts data reads (demand & prefetch) that miss the L2 cache.
B7.01.MSR_RSP0=0x3600003091.TakenAlone OFFCORE_RESPONSE.ANY_DATA_RD.L2_MISS.ANY

# Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that miss the L2 cache.
B7.01.MSR_RSP0=0x36000032b7.TakenAlone OFFCORE_RESPONSE.ANY_READ.L2_MISS.ANY

# Counts partial cache line data writes to uncacheable write combining (USWC) memory region  that miss the L2 cache.
B7.01.MSR_RSP0=0x3600004000.TakenAlone OFFCORE_RESPONSE.PARTIAL_STREAMING_STORES.L2_MISS.ANY

# Counts any data writes to uncacheable write combining (USWC) memory region  that miss the L2 cache.
B7.01.MSR_RSP0=0x3600004800.TakenAlone OFFCORE_RESPONSE.STREAMING_STORES.L2_MISS.ANY

# Counts demand cacheable data reads of full cache lines that are outstanding, per cycle, from the time of the L2 miss to when any response is received.
B7.01.MSR_RSP0=0x4000000001.TakenAlone OFFCORE_RESPONSE.DEMAND_DATA_RD.OUTSTANDING

# Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that are outstanding, per cycle, from the time of the L2 miss to when any response is received.
B7.01.MSR_RSP0=0x4000000002.TakenAlone OFFCORE_RESPONSE.DEMAND_RFO.OUTSTANDING

# Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that are outstanding, per cycle, from the time of the L2 miss to when any response is received.
B7.01.MSR_RSP0=0x4000000004.TakenAlone OFFCORE_RESPONSE.DEMAND_CODE_RD.OUTSTANDING