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nanoBench/configs/cfg_IceLake_all.txt
Andreas Abel 6e63f0404b Ice Lake support
2019-11-08 15:57:52 +01:00

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# Performance monitoring events for processors based on the Ice Lake microarchitecture.
# Applies to processors with DisplayFamily_DisplayModel of 06_7DH and 06_7EH.
# See Table 19-5 of Intel's "System Programming Guide" (May 2019)
00.01 INST_RETIRED.ANY
00.01 INST_RETIRED.PREC_DIST
00.02 CPU_CLK_UNHALTED.THREAD
00.03 CPU_CLK_UNHALTED.REF_TSC
00.04 TOPDOWN.SLOTS
03.02 LD_BLOCKS.STORE_FORWARD
03.08 LD_BLOCKS.NO_SR
07.01 LD_BLOCKS_PARTIAL.ADDRESS_ALIAS
08.02 DTLB_LOAD_MISSES.WALK_COMPLETED_4K
08.04 DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M
08.0E DTLB_LOAD_MISSES.WALK_COMPLETED
08.10 DTLB_LOAD_MISSES.WALK_PENDING
08.10 DTLB_LOAD_MISSES.WALK_ACTIVE
08.20 DTLB_LOAD_MISSES.STLB_HIT
0D.01 INT_MISC.RECOVERY_CYCLES
0D.03 INT_MISC.ALL_RECOVERY_CYCLES
0D.80 INT_MISC.CLEAR_RESTEER_CYCLES
0E.01 UOPS_ISSUED.ANY
0E.01 UOPS_ISSUED.STALL_CYCLES
14.09 ARITH.DIVIDER_ACTIVE
24.21 L2_RQSTS.DEMAND_DATA_RD_MISS
24.22 L2_RQSTS.RFO_MISS
24.24 L2_RQSTS.CODE_RD_MISS
24.27 L2_RQSTS.ALL_DEMAND_MISS
24.28 L2_RQSTS.SWPF_MISS
24.C1 L2_RQSTS.DEMAND_DATA_RD_HIT
24.C2 L2_RQSTS.RFO_HIT
24.C4 L2_RQSTS.CODE_RD_HIT
24.C8 L2_RQSTS.SWPF_HIT
24.E1 L2_RQSTS.ALL_DEMAND_DATA_RD
24.E2 L2_RQSTS.ALL_RFO
24.E4 L2_RQSTS.ALL_CODE_RD
24.E7 L2_RQSTS.ALL_DEMAND_REFERENCES
28.07 CORE_POWER.LVL0_TURBO_LICENSE
28.18 CORE_POWER.LVL1_TURBO_LICENSE
28.20 CORE_POWER.LVL2_TURBO_LICENSE
32.01 SW_PREFETCH_ACCESS.NTA
32.02 SW_PREFETCH_ACCESS.T0
32.04 SW_PREFETCH_ACCESS.T1_T2
32.08 SW_PREFETCH_ACCESS.PREFETCHW
3C.00 CPU_CLK_UNHALTED.THREAD_P
3C.01 CPU_CLK_UNHALTED.REF_XCLK
3C.02 CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE
48.01 L1D_PEND_MISS.PENDING
48.01 L1D_PEND_MISS.PENDING_CYCLES
48.02 L1D_PEND_MISS.FB_FULL
48.02 L1D_PEND_MISS.FB_FULL_PERIODS
48.04 L1D_PEND_MISS.L2_STALL
49.02 DTLB_STORE_MISSES.WALK_COMPLETED_4K
49.04 DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M
49.0E DTLB_STORE_MISSES.WALK_COMPLETED
49.10 DTLB_STORE_MISSES.WALK_PENDING
49.10 DTLB_STORE_MISSES.WALK_ACTIVE
49.20 DTLB_STORE_MISSES.STLB_HIT
4C.01 LOAD_HIT_PREFETCH.SWPF
51.01 L1D.REPLACEMENT
54.01 TX_MEM.ABORT_CONFLICT
54.02 TX_MEM.ABORT_CAPACITY_WRITE
54.04 TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK
54.08 TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY
54.10 TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH
54.20 TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGN
54.40 TX_MEM.HLE_ELISION_BUFFER_FULL
5D.02 TX_EXEC.MISC2
5D.04 TX_EXEC.MISC3
5E.01 RS_EVENTS.EMPTY_CYCLES
5E.01 RS_EVENTS.EMPTY_END
60.04 OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_R
60.08 OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD
60.08 OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD
79.04 IDQ.MITE_UOPS
79.04 IDQ.MITE_CYCLES_OK
79.04 IDQ.MITE_CYCLES_ANY
79.08 IDQ.DSB_UOPS
79.08 IDQ.DSB_CYCLES_OK
79.08 IDQ.DSB_CYCLES_ANY
79.30 IDQ.MS_SWITCHES
79.30 IDQ.MS_UOPS
79.30 IDQ.MS_CYCLES_ANY
80.04 ICACHE_16B.IFDATA_STALL
83.01 ICACHE_64B.IFTAG_HIT
83.02 ICACHE_64B.IFTAG_MISS
83.04 ICACHE_64B.IFTAG_STALL
85.02 ITLB_MISSES.WALK_COMPLETED_4K
85.04 ITLB_MISSES.WALK_COMPLETED_2M_4M
85.0E ITLB_MISSES.WALK_COMPLETED
85.10 ITLB_MISSES.WALK_PENDING
85.10 ITLB_MISSES.WALK_ACTIVE
85.20 ITLB_MISSES.STLB_HIT
87.01 ILD_STALL.LCP
9C.01 IDQ_UOPS_NOT_DELIVERED.CORE
9C.01 IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE
9C.01 IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK
A1.01 UOPS_DISPATCHED.PORT_0
A1.02 UOPS_DISPATCHED.PORT_1
A1.04 UOPS_DISPATCHED.PORT_2_3
A1.10 UOPS_DISPATCHED.PORT_4_9
A1.20 UOPS_DISPATCHED.PORT_5
A1.40 UOPS_DISPATCHED.PORT_6
A1.80 UOPS_DISPATCHED.PORT_7_8
A2.02 RESOURCE_STALLS.SCOREBOARD
A2.08 RESOURCE_STALLS.SB
A3.01 CYCLE_ACTIVITY.CYCLES_L2_MISS
A3.02 CYCLE_ACTIVITY.CYCLES_L3_MISS
A3.04 CYCLE_ACTIVITY.STALLS_TOTAL
A3.05 CYCLE_ACTIVITY.STALLS_L2_MISS
A3.06 CYCLE_ACTIVITY.STALLS_L3_MISS
A3.08 CYCLE_ACTIVITY.CYCLES_L1D_MISS
A3.0C CYCLE_ACTIVITY.STALLS_L1D_MISS
A3.10 CYCLE_ACTIVITY.CYCLES_MEM_ANY
A3.14 CYCLE_ACTIVITY.STALLS_MEM_ANY
A4.01 TOPDOWN.SLOTS_P
A4.02 TOPDOWN.BACKEND_BOUND_SLOTS
A6.02 EXE_ACTIVITY.1_PORTS_UTIL
A6.04 EXE_ACTIVITY.2_PORTS_UTIL
A6.40 EXE_ACTIVITY.BOUND_ON_STORES
A6.80 EXE_ACTIVITY.EXE_BOUND_0_PORTS
A8.01 LSD.UOPS
A8.01 LSD.CYCLES_ACTIVE
A8.01 LSD.CYCLES_OK
AB.02 DSB2MITE_SWITCHES.PENALTY_CYCLES
AE.01 ITLB.ITLB_FLUSH
B0.01 OFFCORE_REQUESTS.DEMAND_DATA_RD
B0.04 OFFCORE_REQUESTS.DEMAND_RFO
B0.08 OFFCORE_REQUESTS.ALL_DATA_RD
B0.10 OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD
B0.80 OFFCORE_REQUESTS.ALL_REQUESTS
B1.01 UOPS_EXECUTED.THREAD
B1.01 UOPS_EXECUTED.STALL_CYCLES
B1.01 UOPS_EXECUTED.CYCLES_GE_1
B1.01 UOPS_EXECUTED.CYCLES_GE_2
B1.01 UOPS_EXECUTED.CYCLES_GE_3
B1.01 UOPS_EXECUTED.CYCLES_GE_4
B1.02 UOPS_EXECUTED.CORE
B1.02 UOPS_EXECUTED.CORE_CYCLES_GE_1
B1.02 UOPS_EXECUTED.CORE_CYCLES_GE_2
B1.02 UOPS_EXECUTED.CORE_CYCLES_GE_3
B1.02 UOPS_EXECUTED.CORE_CYCLES_GE_4
B1.10 UOPS_EXECUTED.X87
BD.01 TLB_FLUSH.DTLB_THREAD
BD.20 TLB_FLUSH.STLB_ANY
C0.00 INST_RETIRED.ANY_P
C1.02 ASSISTS.FP
C1.07 ASSISTS.ANY
C2.02 UOPS_RETIRED.TOTAL_CYCLES
C2.02 UOPS_RETIRED.SLOTS
C3.01 MACHINE_CLEARS.COUNT
C3.02 MACHINE_CLEARS.MEMORY_ORDERING
C3.04 MACHINE_CLEARS.SMC
C4.00 BR_INST_RETIRED.ALL_BRANCHES
C4.01 BR_INST_RETIRED.COND_TAKEN
C4.02 BR_INST_RETIRED.NEAR_CALL
C4.08 BR_INST_RETIRED.NEAR_RETURN
C4.10 BR_INST_RETIRED.COND_NTAKEN
C4.11 BR_INST_RETIRED.COND
C4.20 BR_INST_RETIRED.NEAR_TAKEN
C4.40 BR_INST_RETIRED.FAR_BRANCH
C4.80 BR_INST_RETIRED.INDIRECT
C5.00 BR_MISP_RETIRED.ALL_BRANCHES
C5.01 BR_MISP_RETIRED.COND_TAKEN
C5.11 BR_MISP_RETIRED.COND
C5.20 BR_MISP_RETIRED.NEAR_TAKEN
C5.80 BR_MISP_RETIRED.INDIRECT
C6.01 FRONTEND_RETIRED.DSB_MISS
C6.01 FRONTEND_RETIRED.L1I_MISS
C6.01 FRONTEND_RETIRED.L2_MISS
C6.01 FRONTEND_RETIRED.ITLB_MISS
C6.01 FRONTEND_RETIRED.STLB_MISS
C6.01 FRONTEND_RETIRED.LATENCY_GE_2
C6.01 FRONTEND_RETIRED.LATENCY_GE_4
C6.01 FRONTEND_RETIRED.LATENCY_GE_8
C6.01 FRONTEND_RETIRED.LATENCY_GE_16
C6.01 FRONTEND_RETIRED.LATENCY_GE_32
C6.01 FRONTEND_RETIRED.LATENCY_GE_64
C6.01 FRONTEND_RETIRED.LATENCY_GE_128
C6.01 FRONTEND_RETIRED.LATENCY_GE_256
C6.01 FRONTEND_RETIRED.LATENCY_GE_512
C6.01 FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1
C7.01 FP_ARITH_INST_RETIRED.SCALAR_DOUBLE
C7.02 FP_ARITH_INST_RETIRED.SCALAR_SINGLE
C7.04 FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE
C7.08 FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE
C7.10 FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE
C7.20 FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE
C7.40 FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE
C7.80 FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE
C8.01 HLE_RETIRED.START
C8.02 HLE_RETIRED.COMMIT
C8.04 HLE_RETIRED.ABORTED
C8.08 HLE_RETIRED.ABORTED_MEM
C8.20 HLE_RETIRED.ABORTED_UNFRIENDLY
C8.80 HLE_RETIRED.ABORTED_EVENTS
C9.01 RTM_RETIRED.START
C9.02 RTM_RETIRED.COMMIT
C9.04 RTM_RETIRED.ABORTED
C9.08 RTM_RETIRED.ABORTED_MEM
C9.20 RTM_RETIRED.ABORTED_UNFRIENDLY
C9.40 RTM_RETIRED.ABORTED_MEMTYPE
C9.80 RTM_RETIRED.ABORTED_EVENTS
CC.20 MISC_RETIRED.LBR_INSERTS
CC.40 MISC_RETIRED.PAUSE_INST
CD.01 MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4
CD.01 MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8
CD.01 MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16
CD.01 MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32
CD.01 MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64
CD.01 MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128
CD.01 MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256
CD.01 MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512
D0.12 MEM_INST_RETIRED.STLB_MISS_STORES
D0.41 MEM_INST_RETIRED.SPLIT_LOADS
D0.81 MEM_INST_RETIRED.ALL_LOADS
D0.82 MEM_INST_RETIRED.ALL_STORES
D1.01 MEM_LOAD_RETIRED.L1_HIT
D1.02 MEM_LOAD_RETIRED.L2_HIT
D1.04 MEM_LOAD_RETIRED.L3_HIT
D1.08 MEM_LOAD_RETIRED.L1_MISS
D1.10 MEM_LOAD_RETIRED.L2_MISS
D1.20 MEM_LOAD_RETIRED.L3_MISS
D1.40 MEM_LOAD_RETIRED.FB_HIT
D2.01 MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS
D2.02 MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT
D2.04 MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM
D2.08 MEM_LOAD_L3_HIT_RETIRED.XSNP_NONE
E6.01 BACLEARS.ANY
EC.02 CPU_CLK_UNHALTED.DISTRIBUTED
F1.1F L2_LINES_IN.ALL
F4.04 SQ_MISC.SQ_FULL
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