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233 lines
8.1 KiB
Plaintext
233 lines
8.1 KiB
Plaintext
# Performance monitoring events for processors based on the Haswell microarchitecture.
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# Applies to processors with DisplayFamily_DisplayModel of 06_3CH, 06_45H and 06_46H.
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# See Table 19-10 of Intel's "System Programming Guide" (Jan. 2019)
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03.02 LD_BLOCKS.STORE_FORWARD
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03.08 LD_BLOCKS.NO_SR
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05.01 MISALIGN_MEM_REF.LOADS
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05.02 MISALIGN_MEM_REF.STORES
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07.01 LD_BLOCKS_PARTIAL.ADDRESS_ALIAS
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08.01 DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK
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08.02 DTLB_LOAD_MISSES.WALK_COMPLETED_4K
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08.04 DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M
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08.0E DTLB_LOAD_MISSES.WALK_COMPLETED
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08.10 DTLB_LOAD_MISSES.WALK_DURATION
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08.20 DTLB_LOAD_MISSES.STLB_HIT_4K
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08.40 DTLB_LOAD_MISSES.STLB_HIT_2M
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08.60 DTLB_LOAD_MISSES.STLB_HIT
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08.80 DTLB_LOAD_MISSES.PDE_CACHE_MISS
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0D.03.CMSK=1 INT_MISC.RECOVERY_CYCLES
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0E.01 UOPS_ISSUED.ANY
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0E.10 UOPS_ISSUED.FLAGS_MERGE
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0E.20 UOPS_ISSUED.SLOW_LEA
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0E.40 UOPS_ISSUED.SiNGLE_MUL
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24.21 L2_RQSTS.DEMAND_DATA_RD_MISS
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24.41 L2_RQSTS.DEMAND_DATA_RD_HIT
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24.E1 L2_RQSTS.ALL_DEMAND_DATA_RD
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24.42 L2_RQSTS.RFO_HIT
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24.22 L2_RQSTS.RFO_MISS
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24.E2 L2_RQSTS.ALL_RFO
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24.44 L2_RQSTS.CODE_RD_HIT
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24.24 L2_RQSTS.CODE_RD_MISS
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24.27 L2_RQSTS.ALL_DEMAND_MISS
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24.E7 L2_RQSTS.ALL_DEMAND_REFERENCES
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24.E4 L2_RQSTS.ALL_CODE_RD
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24.50 L2_RQSTS.L2_PF_HIT
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24.30 L2_RQSTS.L2_PF_MISS
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24.F8 L2_RQSTS.ALL_PF
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24.3F L2_RQSTS.MISS
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24.FF L2_RQSTS.REFERENCES
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27.50 L2_DEMAND_RQSTS.WB_HIT
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2E.4F LONGEST_LAT_CACHE.REFERENCE
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2E.41 LONGEST_LAT_CACHE.MISS
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3C.00 CPU_CLK_UNHALTED.THREAD_P
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3C.01 CPU_CLK_THREAD_UNHALTED.REF_XCLK
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48.01.CTR=2 L1D_PEND_MISS.PENDING
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49.01 DTLB_STORE_MISSES.MISS_CAUSES_A_WALK
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49.02 DTLB_STORE_MISSES.WALK_COMPLETED_4K
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49.04 DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M
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49.0E DTLB_STORE_MISSES.WALK_COMPLETED
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49.10 DTLB_STORE_MISSES.WALK_DURATION
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49.20 DTLB_STORE_MISSES.STLB_HIT_4K
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49.40 DTLB_STORE_MISSES.STLB_HIT_2M
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49.60 DTLB_STORE_MISSES.STLB_HIT
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49.80 DTLB_STORE_MISSES.PDE_CACHE_MISS
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4C.01 LOAD_HIT_PRE.SW_PF
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4C.02 LOAD_HIT_PRE.HW_PF
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51.01 L1D.REPLACEMENT
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58.04 MOVE_ELIMINATION.INT_NOT_ELIMINATED
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58.08 MOVE_ELIMINATION.SIMD_NOT_ELIMINATED
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58.01 MOVE_ELIMINATION.INT_ELIMINATED
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58.02 MOVE_ELIMINATION.SIMD_ELIMINATED
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5C.01 CPL_CYCLES.RING0
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5C.02 CPL_CYCLES.RING123
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5E.01 RS_EVENTS.EMPTY_CYCLES
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60.01 OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD
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60.02 OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD
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60.04 OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO
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60.08 OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD
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63.01 LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION
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63.02 LOCK_CYCLES.CACHE_LOCK_DURATION
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79.02 IDQ.EMPTY
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79.04 IDQ.MITE_UOPS
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79.08 IDQ.DSB_UOPS
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79.10 IDQ.MS_DSB_UOPS
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79.20 IDQ.MS_MITE_UOPS
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79.30 IDQ.MS_UOPS
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79.18.CMSK=1 IDQ.ALL_DSB_CYCLES_ANY_UOPS
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79.18.CMSK=4 IDQ.ALL_DSB_CYCLES_4_UOPS
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79.24.CMSK=1 IDQ.ALL_MITE_CYCLES_ANY_UOPS
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79.24.CMSK=4 IDQ.ALL_MITE_CYCLES_4_UOPS
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79.3C IDQ.MITE_ALL_UOPS
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80.02 ICACHE.MISSES
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85.01 ITLB_MISSES.MISS_CAUSES_A_WALK
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85.02 ITLB_MISSES.WALK_COMPLETED_4K
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85.04 ITLB_MISSES.WALK_COMPLETED_2M_4M
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85.0E ITLB_MISSES.WALK_COMPLETED
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85.10 ITLB_MISSES.WALK_DURATION
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85.20 ITLB_MISSES.STLB_HIT_4K
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85.40 ITLB_MISSES.STLB_HIT_2M
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85.60 ITLB_MISSES.STLB_HIT
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87.01 ILD_STALL.LCP
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87.04 ILD_STALL.IQ_FULL
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88.01 BR_INST_EXEC.COND
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88.02 BR_INST_EXEC.DIRECT_JMP
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88.04 BR_INST_EXEC.INDIRECT_JMP_NON_CALL_RET
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88.08 BR_INST_EXEC.RETURN_NEAR
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88.10 BR_INST_EXEC.DIRECT_NEAR_CALL
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88.20 BR_INST_EXEC.INDIRECT_NEAR_CALL
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88.40 BR_INST_EXEC.NONTAKEN
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88.80 BR_INST_EXEC.TAKEN
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88.FF BR_INST_EXEC.ALL_BRANCHES
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89.01 BR_MISP_EXEC.COND
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89.04 BR_MISP_EXEC.INDIRECT_JMP_NON_CALL_RET
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89.08 BR_MISP_EXEC.RETURN_NEAR
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89.10 BR_MISP_EXEC.DIRECT_NEAR_CALL
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89.20 BR_MISP_EXEC.INDIRECT_NEAR_CALL
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89.40 BR_MISP_EXEC.NONTAKEN
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89.80 BR_MISP_EXEC.TAKEN
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89.FF BR_MISP_EXEC.ALL_BRANCHES
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9C.01 IDQ_UOPS_NOT_DELIVERED.CORE
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A1.01 UOPS_EXECUTED_PORT.PORT_0
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A1.02 UOPS_EXECUTED_PORT.PORT_1
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A1.04 UOPS_EXECUTED_PORT.PORT_2
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A1.08 UOPS_EXECUTED_PORT.PORT_3
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A1.10 UOPS_EXECUTED_PORT.PORT_4
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A1.20 UOPS_EXECUTED_PORT.PORT_5
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A1.40 UOPS_EXECUTED_PORT.PORT_6
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A1.80 UOPS_EXECUTED_PORT.PORT_7
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A2.01 RESOURCE_STALLS.ANY
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A2.04 RESOURCE_STALLS.RS
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A2.08 RESOURCE_STALLS.SB
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A2.10 RESOURCE_STALLS.ROB
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A3.01 CYCLE_ACTIVITY.CYCLES_L2_PENDING
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A3.02 CYCLE_ACTIVITY.CYCLES_LDM_PENDING
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A3.05 CYCLE_ACTIVITY.STALLS_L2_PENDING
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A3.08.CTR=2 CYCLE_ACTIVITY.CYCLES_L1D_PENDING
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A3.0C.CTR=2 CYCLE_ACTIVITY.STALLS_L1D_PENDING
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A8.01 LSD.UOPS
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AE.01 ITLB.ITLB_FLUSH
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B0.01 OFFCORE_REQUESTS.DEMAND_DATA_RD
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B0.02 OFFCORE_REQUESTS.DEMAND_CODE_RD
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B0.04 OFFCORE_REQUESTS.DEMAND_RFO
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B0.08 OFFCORE_REQUESTS.ALL_DATA_RD
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B1.02 UOPS_EXECUTED.CORE
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B7.01.CTR=0.MSR_RSP0=0x10001 OFF_CORE_RESPONSE_0.DMND_DATA_RD
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B7.01.CTR=0.MSR_RSP0=0x10002 OFF_CORE_RESPONSE_0.DMND_RFO
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B7.01.CTR=0.MSR_RSP0=0x10004 OFF_CORE_RESPONSE_0.DMND_IFETCH
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B7.01.CTR=0.MSR_RSP0=0x10008 OFF_CORE_RESPONSE_0.COREWB
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B7.01.CTR=0.MSR_RSP0=0x10010 OFF_CORE_RESPONSE_0.PF_DATA_RD
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B7.01.CTR=0.MSR_RSP0=0x10020 OFF_CORE_RESPONSE_0.PF_RFO
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B7.01.CTR=0.MSR_RSP0=0x10040 OFF_CORE_RESPONSE_0.PF_IFETCH
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B7.01.CTR=0.MSR_RSP0=0x10080 OFF_CORE_RESPONSE_0.PF_L3_DATA_RD
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B7.01.CTR=0.MSR_RSP0=0x10100 OFF_CORE_RESPONSE_0.PF_L3_RFO
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B7.01.CTR=0.MSR_RSP0=0x10200 OFF_CORE_RESPONSE_0.PF_L3_CODE_RD
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B7.01.CTR=0.MSR_RSP0=0x10400 OFF_CORE_RESPONSE_0.SPLIT_LOCK_UC_LOCK
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B7.01.CTR=0.MSR_RSP0=0x10800 OFF_CORE_RESPONSE_0.STRM_ST
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B7.01.CTR=0.MSR_RSP0=0x18000 OFF_CORE_RESPONSE_0.OTHER
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BB.01.CTR=1.MSR_RSP1=0x10001 OFF_CORE_RESPONSE_1.DMND_DATA_RD
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BB.01.CTR=1.MSR_RSP1=0x10002 OFF_CORE_RESPONSE_1.DMND_RFO
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BB.01.CTR=1.MSR_RSP1=0x10004 OFF_CORE_RESPONSE_1.DMND_IFETCH
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BB.01.CTR=1.MSR_RSP1=0x10008 OFF_CORE_RESPONSE_1.COREWB
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BB.01.CTR=1.MSR_RSP1=0x10010 OFF_CORE_RESPONSE_1.PF_DATA_RD
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BB.01.CTR=1.MSR_RSP1=0x10020 OFF_CORE_RESPONSE_1.PF_RFO
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BB.01.CTR=1.MSR_RSP1=0x10040 OFF_CORE_RESPONSE_1.PF_IFETCH
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BB.01.CTR=1.MSR_RSP1=0x10080 OFF_CORE_RESPONSE_1.PF_L3_DATA_RD
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BB.01.CTR=1.MSR_RSP1=0x10100 OFF_CORE_RESPONSE_1.PF_L3_RFO
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BB.01.CTR=1.MSR_RSP1=0x10200 OFF_CORE_RESPONSE_1.PF_L3_CODE_RD
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BB.01.CTR=1.MSR_RSP1=0x10400 OFF_CORE_RESPONSE_1.SPLIT_LOCK_UC_LOCK
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BB.01.CTR=1.MSR_RSP1=0x10800 OFF_CORE_RESPONSE_1.STRM_ST
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BB.01.CTR=1.MSR_RSP1=0x18000 OFF_CORE_RESPONSE_1.OTHER
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BC.11 PAGE_WALKER_LOADS.DTLB_L1
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BC.21 PAGE_WALKER_LOADS.ITLB_L1
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BC.12 PAGE_WALKER_LOADS.DTLB_L2
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BC.22 PAGE_WALKER_LOADS.ITLB_L2
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BC.14 PAGE_WALKER_LOADS.DTLB_L3
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BC.24 PAGE_WALKER_LOADS.ITLB_L3
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BC.18 PAGE_WALKER_LOADS.DTLB_MEMORY
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BC.28 PAGE_WALKER_LOADS.ITLB_MEMORY
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BD.01 TLB_FLUSH.DTLB_THREAD
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BD.20 TLB_FLUSH.STLB_ANY
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C0.00 INST_RETIRED.ANY_P
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C0.01.CTR=1 INST_RETIRED.PREC_DIST
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C1.08 OTHER_ASSISTS.AVX_TO_SSE
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C1.10 OTHER_ASSISTS.SSE_TO_AVX
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C1.40 OTHER_ASSISTS.ANY_WB_ASSIST
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C2.01 UOPS_RETIRED.ALL
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C2.02 UOPS_RETIRED.RETIRE_SLOTS
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C3.02 MACHINE_CLEARS.MEMORY_ORDERING
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C3.04 MACHINE_CLEARS.SMC
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C3.20 MACHINE_CLEARS.MASKMOV
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C4.00 BR_INST_RETIRED.ALL_BRANCHES
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C4.01 BR_INST_RETIRED.CONDITIONAL
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C4.02 BR_INST_RETIRED.NEAR_CALL
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C4.04 BR_INST_RETIRED.ALL_BRANCHES
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C4.08 BR_INST_RETIRED.NEAR_RETURN
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C4.10 BR_INST_RETIRED.NOT_TAKEN
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C4.20 BR_INST_RETIRED.NEAR_TAKEN
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C4.40 BR_INST_RETIRED.FAR_BRANCH
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C5.00 BR_MISP_RETIRED.ALL_BRANCHES
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C5.01 BR_MISP_RETIRED.CONDITIONAL
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C5.04 BR_MISP_RETIRED.ALL_BRANCHES
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C5.20 BR_MISP_RETIRED.NEAR_TAKEN
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CA.02 FP_ASSIST.X87_OUTPUT
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CA.04 FP_ASSIST.X87_INPUT
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CA.08 FP_ASSIST.SIMD_OUTPUT
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CA.10 FP_ASSIST.SIMD_INPUT
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CA.1E FP_ASSIST.ANY
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CC.20 ROB_MISC_EVENTS.LBR_INSERTS
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CD.01.MSR_3F6H=10 MEM_TRANS_RETIRED.LOAD_LATENCY
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D0.11 MEM_UOPS_RETIRED.STLB_MISS_LOADS
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D0.12 MEM_UOPS_RETIRED.STLB_MISS_STORES
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D0.21 MEM_UOPS_RETIRED.LOCK_LOADS
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D0.41 MEM_UOPS_RETIRED.SPLIT_LOADS
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D0.42 MEM_UOPS_RETIRED.SPLIT_STORES
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D0.81 MEM_UOPS_RETIRED.ALL_LOADS
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D0.82 MEM_UOPS_RETIRED.ALL_STORES
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D1.01 MEM_LOAD_UOPS_RETIRED.L1_HIT
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D1.02 MEM_LOAD_UOPS_RETIRED.L2_HIT
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D1.04 MEM_LOAD_UOPS_RETIRED.L3_HIT
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D1.08 MEM_LOAD_UOPS_RETIRED.L1_MISS
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D1.10 MEM_LOAD_UOPS_RETIRED.L2_MISS
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D1.20 MEM_LOAD_UOPS_RETIRED.L3_MISS
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D1.40 MEM_LOAD_UOPS_RETIRED.HIT_LFB
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D2.01 MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS
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D2.02 MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT
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D2.04 MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM
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D2.08 MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_NONE
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D3.01 MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM
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E6.1F BACLEARS.ANY
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F0.01 L2_TRANS.DEMAND_DATA_RD
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F0.02 L2_TRANS.RFO
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F0.04 L2_TRANS.CODE_RD
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F0.08 L2_TRANS.ALL_PF
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F0.10 L2_TRANS.L1D_WB
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F0.20 L2_TRANS.L2_FILL
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F0.40 L2_TRANS.L2_WB
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F0.80 L2_TRANS.ALL_REQUESTS
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F1.01 L2_LINES_IN.I
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F1.02 L2_LINES_IN.S
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F1.04 L2_LINES_IN.E
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F1.07 L2_LINES_IN.ALL
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F2.05 L2_LINES_OUT.DEMAND_CLEAN
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F2.06 L2_LINES_OUT.DEMAND_DIRTY |