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23 lines
769 B
Plaintext
23 lines
769 B
Plaintext
# Performance monitoring events for processors based on the Ice Lake microarchitecture.
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# Applies to processors with DisplayFamily_DisplayModel of 06_7DH and 06_7EH.
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# See Table 19-5 of Intel's "System Programming Guide" (May 2019)
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3C.00 CORE_CYCLES
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C0.00 INST_RETIRED
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0E.01 UOPS_ISSUED
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B1.01 UOPS_EXECUTED
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A1.01 UOPS_DISPATCHED.PORT_0
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A1.02 UOPS_DISPATCHED.PORT_1
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A1.04 UOPS_DISPATCHED.PORT_2_3
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A1.10 UOPS_DISPATCHED.PORT_4_9
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A1.20 UOPS_DISPATCHED.PORT_5
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A1.40 UOPS_DISPATCHED.PORT_6
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A1.80 UOPS_DISPATCHED.PORT_7_8
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C4.00 BR_INST_RETIRED.ALL_BRANCHES
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C5.00 BR_MISP_RETIRED.ALL_BRANCHES
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D1.01 MEM_LOAD_RETIRED.L1_HIT
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D1.08 MEM_LOAD_RETIRED.L1_MISS
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D1.02 MEM_LOAD_RETIRED.L2_HIT
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D1.10 MEM_LOAD_RETIRED.L2_MISS
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D1.04 MEM_LOAD_RETIRED.L3_HIT
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D1.20 MEM_LOAD_RETIRED.L3_MISS |