mirror of
https://github.com/andreas-abel/nanoBench.git
synced 2026-01-04 11:30:06 +01:00
141 lines
5.2 KiB
Python
141 lines
5.2 KiB
Python
GPRegs = {'AH', 'AL', 'AX', 'BH', 'BL', 'BP', 'BPL', 'BX', 'CH', 'CL', 'CX', 'DH', 'DI', 'DIL', 'DL', 'DX', 'EAX',
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'EBP', 'EBX', 'ECX', 'EDI', 'EDX', 'ESI', 'ESP', 'R10', 'R10B', 'R10D', 'R10W', 'R11', 'R11B', 'R11D', 'R11W', 'R12',
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'R12B', 'R12D', 'R12W', 'R13', 'R13B', 'R13D', 'R13W', 'R14', 'R14B', 'R14D', 'R14W', 'R15', 'R15B', 'R15D', 'R15W',
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'R8', 'R8B', 'R8D', 'R8W', 'R9', 'R9B', 'R9D', 'R9W', 'RAX', 'RBP', 'RBX', 'RCX', 'RDI', 'RDX', 'RSI', 'RSP', 'SI',
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'SIL', 'SP', 'SPL'}
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STATUSFLAGS = {'CF', 'PF', 'AF', 'ZF', 'SF', 'OF'}
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STATUSFLAGS_noAF = {'CF', 'PF', 'ZF', 'SF', 'OF'}
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def regTo64(reg):
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if 'AX' in reg or 'AH' in reg or 'AL' in reg: return 'RAX'
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if 'BX' in reg or 'BH' in reg or 'BL' in reg: return 'RBX'
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if 'CX' in reg or 'CH' in reg or 'CL' in reg: return 'RCX'
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if 'DX' in reg or 'DH' in reg or 'DL' in reg: return 'RDX'
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if 'SP' in reg: return 'RSP'
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if 'BP' in reg: return 'RBP'
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if 'SI' in reg: return 'RSI'
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if 'DI' in reg: return 'RDI'
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if '8' in reg: return 'R8'
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if '9' in reg: return 'R9'
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if '10' in reg: return 'R10'
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if '11' in reg: return 'R11'
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if '12' in reg: return 'R12'
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if '13' in reg: return 'R13'
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if '14' in reg: return 'R14'
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if '15' in reg: return 'R15'
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def regTo32(reg):
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if 'AX' in reg or 'AH' in reg or 'AL' in reg: return 'EAX'
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if 'BX' in reg or 'BH' in reg or 'BL' in reg: return 'EBX'
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if 'CX' in reg or 'CH' in reg or 'CL' in reg: return 'ECX'
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if 'DX' in reg or 'DH' in reg or 'DL' in reg: return 'EDX'
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if 'SP' in reg: return 'ESP'
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if 'BP' in reg: return 'EBP'
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if 'SI' in reg: return 'ESI'
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if 'DI' in reg: return 'EDI'
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if '8' in reg: return 'R8D'
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if '9' in reg: return 'R9D'
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if '10' in reg: return 'R10D'
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if '11' in reg: return 'R11D'
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if '12' in reg: return 'R12D'
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if '13' in reg: return 'R13D'
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if '14' in reg: return 'R14D'
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if '15' in reg: return 'R15D'
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def regTo16(reg):
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if 'AX' in reg or 'AH' in reg or 'AL' in reg: return 'AX'
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if 'BX' in reg or 'BH' in reg or 'BL' in reg: return 'BX'
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if 'CX' in reg or 'CH' in reg or 'CL' in reg: return 'CX'
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if 'DX' in reg or 'DH' in reg or 'DL' in reg: return 'DX'
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if 'SP' in reg: return 'SP'
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if 'BP' in reg: return 'BP'
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if 'SI' in reg: return 'SI'
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if 'DI' in reg: return 'DI'
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if '8' in reg: return 'R8W'
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if '9' in reg: return 'R9W'
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if '10' in reg: return 'R10W'
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if '11' in reg: return 'R11W'
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if '12' in reg: return 'R12W'
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if '13' in reg: return 'R13W'
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if '14' in reg: return 'R14W'
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if '15' in reg: return 'R15W'
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def regTo8(reg):
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if 'AX' in reg or 'AH' in reg or 'AL' in reg: return 'AL'
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if 'BX' in reg or 'BH' in reg or 'BL' in reg: return 'BL'
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if 'CX' in reg or 'CH' in reg or 'CL' in reg: return 'CL'
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if 'DX' in reg or 'DH' in reg or 'DL' in reg: return 'DL'
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if 'SP' in reg: return 'SPL'
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if 'BP' in reg: return 'BPL'
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if 'SI' in reg: return 'SIL'
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if 'DI' in reg: return 'DIL'
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if '8' in reg: return 'R8B'
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if '9' in reg: return 'R9B'
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if '10' in reg: return 'R10B'
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if '11' in reg: return 'R11B'
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if '12' in reg: return 'R12B'
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if '13' in reg: return 'R13B'
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if '14' in reg: return 'R14B'
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if '15' in reg: return 'R15B'
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def regToSize(reg, size):
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if size == 8: return regTo8(reg)
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elif size == 16: return regTo16(reg)
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elif size == 32: return regTo32(reg)
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else: return regTo64(reg)
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# Returns a set of registers that are a part of the register that is provided (e.g., EAX is a part of RAX; RAX is also a part of RAX)
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def getSubRegs(reg):
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subRegs = set()
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subRegs.add(reg)
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if reg in GPRegs:
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regSize = getRegSize(reg)
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if regSize > 8:
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for size in [16, 32, 64]:
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if size > regSize: continue
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subRegs.add(regToSize(reg, size))
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if 'AX' in reg or 'BX' in reg or 'CX' in reg or 'DX' in reg:
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subRegs.add(reg[-2] + 'L')
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subRegs.add(reg[-2] + 'H')
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else:
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subRegs.add(regTo8(reg))
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elif 'ZMM' in reg:
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subRegs.add('Y' + reg[1:])
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subRegs.add('X' + reg[1:])
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elif 'YMM' in reg:
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subRegs.add('X' + reg[1:])
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return subRegs
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# Returns for a GPR the corresponding 64-bit registers, and for a (X|Y|Z)MM register the corresponding XMM register
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def getCanonicalReg(reg):
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if reg in GPRegs:
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return regTo64(reg)
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elif 'MM' in reg:
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return re.sub('^[YZ]', 'X', reg)
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else:
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return reg
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def getRegForMemPrefix(reg, memPrefix):
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return regToSize(reg, getSizeOfMemPrefix(memPrefix))
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def getSizeOfMemPrefix(memPrefix):
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if 'zmmword' in memPrefix: return 512
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elif 'ymmword' in memPrefix: return 256
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elif 'xmmword' in memPrefix: return 128
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elif 'qword' in memPrefix: return 64
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elif 'dword' in memPrefix: return 32
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elif 'word' in memPrefix: return 16
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elif 'byte' in memPrefix: return 8
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else: return -1
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def getRegSize(reg):
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if reg[-1] == 'L' or reg[-1] == 'H' or reg[-1] == 'B': return 8
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elif reg[-1] == 'W' or reg in ['AX', 'BX', 'CX', 'DX', 'SP', 'BP' 'SI', 'DI']: return 16
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elif reg[0] == 'E' or reg[-1] == 'D': return 32
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elif reg in GPRegs: return 64
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elif reg.startswith('MM'): return 64
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elif reg.startswith('XMM'): return 128
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elif reg.startswith('YMM'): return 256
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elif reg.startswith('ZMM'): return 512
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else: return -1 |