mirror of
https://github.com/RRZE-HPC/OSACA.git
synced 2025-12-16 00:50:06 +01:00
added API for external tools
This commit is contained in:
Julian Hammer
@@ -13,35 +13,27 @@ from osaca.param import Register, MemAddr
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class Scheduler(object):
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arch_dict = {'SNB': 6, 'IVB': 6, 'HSW': 8, 'BDW': 8, 'SKL': 8, 'ZEN': 10}
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dv_port_dict = {'SKL': 0, 'ZEN': 3}
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ports = None # type: int
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instrList = None # type: list<list<str,Param[,Param][,Param],str>>,
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dv_ports_dict = {'SKL': [0], 'ZEN': [3]}
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# content of most inner list in instrList: instr, operand(s), instr form
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df = None # type: DataFrame
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# for parallel ld/st in archs with 1 st/cy and >1 ld/cy, able to do 1 st and 1 ld in 1cy
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ld_ports = None # type: list<int>
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# enable flag for parallel ld/st
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en_par_ldst = False # type: boolean
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dv_port = -1 # type: int
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def __init__(self, arch, instruction_list):
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arch = arch.upper()
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try:
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self.ports = self.arch_dict[arch]
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except KeyError:
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print('Architecture not supportet for EU scheduling.', file=sys.stderr)
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print('Architecture not supported for EU scheduling.', file=sys.stderr)
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sys.exit(1)
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# check for parallel ld/st in a cycle
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if arch == 'ZEN':
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self.en_par_ldst = True
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self.ld_ports = [9, 10]
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# check for DV port
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try:
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self.dv_port = self.dv_port_dict[arch]
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except KeyError:
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# no DV port available (yet, new feature in OSACA v0.2)
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# do nothing
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pass
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self.dv_ports = self.dv_ports_dict.get(arch, [])
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self.instrList = instruction_list
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# curr_dir = os.path.realpath(__file__)[:-11]
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osaca_dir = os.path.expanduser('~/.osaca/')
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@@ -68,11 +60,8 @@ class Scheduler(object):
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sched = self.get_head()
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# Initialize ports
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# Add DV port, if it is existing
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tmp_port = 0
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if self.dv_port != -1:
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tmp_port = 1
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occ_ports = [[0] * (self.ports + tmp_port) for x in range(len(self.instrList))]
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port_bndgs = [0] * (self.ports + tmp_port)
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occ_ports = [[0] * (self.ports + len(self.dv_ports)) for x in range(len(self.instrList))]
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port_bndgs = [0] * (self.ports + len(self.dv_ports))
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# Store instruction counter for parallel ld/st
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par_ldst = 0
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# Count the number of store instr if we schedule for an architecture with par ld/st
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@@ -94,9 +83,9 @@ class Scheduler(object):
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except IndexError:
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# Instruction form not in CSV
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if instrForm[0][:3] == 'nop':
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sched += self.get_line(occ_ports[i], '* ' + instrForm[-1])
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sched += self.format_port_occupation_line(occ_ports[i], '* ' + instrForm[-1])
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else:
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sched += self.get_line(occ_ports[i], 'X ' + instrForm[-1])
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sched += self.format_port_occupation_line(occ_ports[i], 'X ' + instrForm[-1])
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continue
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occ_ports[i] = list(tup)
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# Check if it's a ld including instr
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@@ -112,11 +101,11 @@ class Scheduler(object):
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occ_ports[i][port] = '(' + str(occ_ports[i][port]) + ')'
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# Write schedule line
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if len(p_flg) > 0:
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sched += self.get_line(occ_ports[i], p_flg + instrForm[-1])
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sched += self.format_port_occupation_line(occ_ports[i], p_flg + instrForm[-1])
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for port in self.ld_ports:
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occ_ports[i][port] = 0
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else:
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sched += self.get_line(occ_ports[i], instrForm[-1])
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sched += self.format_port_occupation_line(occ_ports[i], instrForm[-1])
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# Add throughput to total port binding
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port_bndgs = list(map(add, port_bndgs, occ_ports[i]))
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if machine_readable:
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@@ -150,9 +139,9 @@ class Scheduler(object):
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except IndexError:
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# Instruction form not in CSV
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if instrForm[0][:3] == 'nop':
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sched += self.get_line(occ_ports[i], '* ' + instrForm[-1])
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sched += self.format_port_occupation_line(occ_ports[i], '* ' + instrForm[-1])
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else:
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sched += self.get_line(occ_ports[i], 'X ' + instrForm[-1])
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sched += self.format_port_occupation_line(occ_ports[i], 'X ' + instrForm[-1])
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continue
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if wTP:
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# Get the occurance of each port from the occupation list
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@@ -176,7 +165,7 @@ class Scheduler(object):
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for j in range(0, self.ports):
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occ_ports[i][j] = t_all.count(j) / variations
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# Write schedule line
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sched += self.get_line(occ_ports[i], instrForm[-1])
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sched += self.format_port_occupation_line(occ_ports[i], instrForm[-1])
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# Add throughput to total port binding
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port_bndgs = list(map(add, port_bndgs, occ_ports[i]))
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return sched, port_bndgs
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@@ -214,7 +203,7 @@ class Scheduler(object):
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raise IndexError()
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except IndexError:
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# Instruction form not in CSV
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sched += self.get_line([0] * self.ports, '* ' + instrForm[-1])
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sched += self.format_port_occupation_line([0] * self.ports, '* ' + instrForm[-1])
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continue
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found = False
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while not found:
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@@ -226,7 +215,7 @@ class Scheduler(object):
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found = True
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good = [entry.LT.values[0] if (j in portOcc) else 0 for j in
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range(0, self.ports)]
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sched += self.get_line(good, instrForm[-1])
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sched += self.format_port_occupation_line(good, instrForm[-1])
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# Add new occupation
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occ_ports = [occ_ports[j] + good[j] for j in range(0, self.ports)]
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break
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@@ -331,22 +320,15 @@ class Scheduler(object):
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str
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String containing the header
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"""
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horiz_line = '-' * 7 * self.ports
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if self.dv_port != -1:
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horiz_line += '-' * 6
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horiz_line += '-\n'
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port_anno = (' ' * int(math.floor((len(horiz_line) - 24) / 2)) + 'Ports Pressure in cycles'
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+ ' ' * int(math.ceil((len(horiz_line) - 24) / 2)) + '\n')
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port_line = ''
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for i in range(0, self.ports):
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port_line += '| {} '.format(i)
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if i == self.dv_port:
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port_line = port_line + '- DV '
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port_line += '|\n'
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head = port_anno + port_line + horiz_line
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return head
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port_names = self.get_port_naming()
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def get_line(self, occ_ports, instr_name):
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port_line = ''.join('|{:^6}'.format(pn) for pn in port_names) + '|\n'
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horiz_line = '-' * (len(port_line) - 1) + '\n'
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port_anno = ' ' * ((len(port_line) - 25) // 2) + 'Ports Pressure in cycles\n'
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return port_anno + port_line + horiz_line
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def format_port_occupation_line(self, occ_ports, instr_name):
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"""
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Create line with port occupation for output.
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@@ -363,24 +345,31 @@ class Scheduler(object):
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String for output containing port scheduling for instr_name
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"""
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line = ''
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for p_num, i in enumerate(occ_ports):
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pipe = '|'
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if isinstance(i, str):
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cycles = i
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i = float(i[1:-1])
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r_space = ''
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for cycles in occ_ports:
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if cycles == 0:
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line += '|' + ' ' * 6
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elif cycles >= 10:
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line += '|{:^6.1f}'.format(cycles)
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else:
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cycles = ' ' if (i == 0) else '%.2f' % float(i)
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r_space = ' '
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if p_num == self.dv_port + 1 and p_num != 0:
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pipe = ' '
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if i >= 10:
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line += pipe + cycles + r_space
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else:
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line += pipe + ' ' + cycles + r_space
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line += '|{:^6.2f}'.format(cycles)
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line += '| ' + instr_name + '\n'
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return line
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def get_port_naming(self):
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"""
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Return list of port names
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:return: list of strings
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"""
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port_names = []
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dv_ports_appended = 0
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for i in range(self.ports):
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port_names.append(str(i))
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if i in self.dv_ports:
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dv_ports_appended += 1
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port_names.append(str(i)+'DV')
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return port_names
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def get_port_binding(self, port_bndg):
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"""
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Create port binding out of scheduling result.
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@@ -395,36 +384,23 @@ class Scheduler(object):
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str
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String containing the port binding graphical output
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"""
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sp_left, sp_right, total = self.get_spaces(port_bndg)
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col_widths = self.get_column_widths(port_bndg)
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header = 'Port Binding in Cycles Per Iteration:\n'
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horiz_line = '-' * 10 + '-' * total + '\n'
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horiz_line = '-' * 10 + '-' * (sum(col_widths) + len(col_widths)) + '\n'
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port_line = '| Port |'
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after_dv = 0
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for i in range(0, self.ports):
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if i == self.dv_port:
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port_line += ' ' * int(sp_left[i]) + str(i) + ' ' * int(sp_right[i]) + '-'
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port_line += ' ' * int(sp_left[i + 1] - 1) + 'DV' + ' ' * int(sp_right[i + 1]) + '|'
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after_dv = 1
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else:
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port_line += (' ' * int(sp_left[i + after_dv]) + str(i)
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+ ' ' * int(sp_right[i + after_dv]))
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port_line += '|'
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for i, port_name in enumerate(self.get_port_naming()):
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port_line += port_name.center(col_widths[i]) + '|'
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port_line += '\n'
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cyc_line = '| Cycles |'
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for i in range(len(port_bndg)):
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pipe = '|' if (i != self.dv_port) else ' '
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cyc = str(round(port_bndg[i], 2))
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cyc_line += ' {} {}'.format(cyc, pipe)
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cyc_line += '{}|'.format(str(round(port_bndg[i], 2)).center(col_widths[i]))
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cyc_line += '\n'
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binding = header + horiz_line + port_line + horiz_line + cyc_line + horiz_line
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return binding
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def get_spaces(self, port_bndg):
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len_list = [len(str(round(x, 2))) + 1 for x in port_bndg]
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total = sum([x + 2 for x in len_list])
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sp_left = [math.ceil(x / 2) for x in len_list]
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sp_right = [math.floor(x / 2) for x in len_list]
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return sp_left, sp_right, total
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def get_column_widths(self, port_bndg):
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return [max(len(str(round(x, 2))), len(name)) + 2
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for x, name in zip(port_bndg, self.get_port_naming())]
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def get_operand_suffix(self, instr_form):
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"""
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@@ -1,6 +1,7 @@
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#!/usr/bin/env python3
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import argparse
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import collections
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import sys
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import os
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import io
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@@ -316,7 +317,40 @@ def strip_assembly(assembly):
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return '\n'.join(asm_lines)
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# TODO replacement for instr_forms entries in OSACA
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# class InstructionForm:
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# def __init__(self, mnemonic, parameters, line=None):
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# self.mnemonic = mnemonic
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# self.parameters = parameters
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# self.line = line
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#
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# @classmethod
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# def from_assembly(cls, line):
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# # Skip clang padding bytes
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# while line.startswith('data32 '):
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# line = line[7:]
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#
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# line_split = line.split()
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# mnemonic = line_split[0]
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# if len(line_split) > 1:
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# parameters = line_split[1:]
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# else:
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# parameters = None
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#
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# return cls(mnemonic, parameters, line)
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#
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# def __str__(self):
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# return line
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#
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# def __repr__(self):
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# return '{}({!r}, {!r}, {!r})'.format(
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# self.__class__.__name__, self.mnemonic, self.parameters, self.line)
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class OSACA(object):
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"""
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A single OSACA analysis.
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"""
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srcCode = None
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tp_list = False
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# Variables for checking lines
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@@ -331,6 +365,13 @@ class OSACA(object):
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VALID_ARCHS = ['SNB', 'IVB', 'HSW', 'BDW', 'SKL', 'ZEN']
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def __init__(self, arch, assembly, extract_with_markers=True):
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"""
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Create and run analysis on assembly for architecture.
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:param arch: architecture abbreviation
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:param assembly: assembly code as string
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:param extract_with_markers: if True, use markers to isolate relavent section
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"""
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# Check architecture
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if arch not in self.VALID_ARCHS:
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raise ValueError("Invalid architecture ({!r}), must be one of {}.".format(
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@@ -353,14 +394,20 @@ class OSACA(object):
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# Check for database for the chosen architecture
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self.df = read_csv(arch)
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# Run analysis
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# Run analysis and populate instr_forms
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self.inspect()
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# Create schedule
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self.schedule = Scheduler(self.arch, self.instr_forms)
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def inspect(self):
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"""
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Run analysis.
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"""
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for line in self.assembly:
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# TODO potential replacement for instr_forms entries in OSACA
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# InstructionForm.from_assembly(line)
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if re.match(r'^[a-zA-Z0-9\_\.]+:$', line):
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continue
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self.check_instr(line)
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@@ -391,8 +438,7 @@ class OSACA(object):
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param_list_types = list(param_list)
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# Check operands and separate them by IMMEDIATE (IMD), REGISTER (REG),
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# MEMORY (MEM) or LABEL(LBL)
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for i in range(len(param_list)):
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op = param_list[i]
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for i, op in enumerate(param_list):
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if len(op) <= 0:
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op = Parameter('NONE')
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elif op[0] == '$':
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@@ -404,10 +450,10 @@ class OSACA(object):
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j = op.index('{')
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opmask = True
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op = Register(op[1:j].strip(" ,"), opmask)
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elif '<' in op or op.startswith('.'):
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elif '<' in op or re.match(r'^([a-zA-Z\._]+[a-zA-Z0-9_\.]*)+$', op):
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op = Parameter('LBL')
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else:
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op = MemAddr(op, )
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op = MemAddr(op)
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param_list[i] = str(op)
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param_list_types[i] = op
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# Add to list
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@@ -464,6 +510,8 @@ class OSACA(object):
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"""
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Creates output of analysed file including a time stamp.
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Used to interface with Kerncraft.
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Parameters
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----------
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tp_list : bool
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@@ -489,17 +537,40 @@ class OSACA(object):
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output += self.create_tp_list(horiz_line)
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if pr_sched:
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output += '\n\n'
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sched = Scheduler(self.arch, self.instr_forms)
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sched_output, port_binding = sched.new_schedule(machine_readable)
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sched_output, port_binding = self.schedule.new_schedule(machine_readable)
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# if machine_readable, we're already done here
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if machine_readable:
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return sched_output
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binding = sched.get_port_binding(port_binding)
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output += sched.get_report_info() + '\n' + binding + '\n\n' + sched_output
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binding = self.schedule.get_port_binding(port_binding)
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output += self.schedule.get_report_info() + '\n' + binding + '\n\n' + sched_output
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block_tp = round(max(port_binding), 2)
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output += 'Total number of estimated throughput: {}\n'.format(block_tp)
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return output
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def get_port_occupation_cycles(self):
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"""
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Build dict with port names and cycles they are occupied during one block execution
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Used to interface with Kerncraft.
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:return: dictionary of ports and cycles
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"""
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sched_output, port_binding = self.schedule.new_schedule()
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return collections.OrderedDict([
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(port_name, port_binding[i])
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for i, port_name in enumerate(self.schedule.get_port_naming())])
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def get_total_throughput(self):
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"""
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Return total cycles estimated per block execution. Including (potential) penalties.
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Used to interface with Kerncraft.
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:return: float of cycles
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"""
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return max(self.get_port_occupation_cycles().values())
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def create_horiz_sep(self):
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"""
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Calculate and return horizontal separator line.
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