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added default load TP and relocation in identifier

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This commit is contained in:
JanLJL
2019-12-18 16:56:20 +01:00
parent 23d270f005
commit 11f91fe9e1
12 changed files with 25 additions and 3 deletions
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1
osaca/data/bdw.yml
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@@ -16,6 +16,7 @@ load_throughput:
- {base: gpr, index: gpr, offset: ~, scale: 8, port_pressure: [[1, '23'], [1, ['2D', '3D']]]}
- {base: gpr, index: gpr, offset: imd, scale: 1, port_pressure: [[1, '23'], [1, ['2D', '3D']]]}
- {base: gpr, index: gpr, offset: imd, scale: 8, port_pressure: [[1, '23'], [1, ['2D', '3D']]]}
load_throughput_default: [[1, '23'], [1, ['2D', '3D']]]
ports: ['0', 0DV, '1', '2', 2D, '3', 3D, '4', '5', '6', '7']
port_model_scheme: |
┌------------------------------------------------------------------------┐

5
osaca/data/csx.yml
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@@ -12,10 +12,15 @@ load_throughput:
- {base: gpr, index: ~, offset: ~, scale: 8, port_pressure: [[1, '23'], [1, ['2D', '3D']]]}
- {base: gpr, index: ~, offset: imd, scale: 1, port_pressure: [[1, '23'], [1, ['2D', '3D']]]}
- {base: gpr, index: ~, offset: imd, scale: 8, port_pressure: [[1, '23'], [1, ['2D', '3D']]]}
- {base: gpr, index: ~, offset: id, scale: 1, port_pressure: [[1, '23'], [1, ['2D', '3D']]]}
- {base: gpr, index: ~, offset: id, scale: 8, port_pressure: [[1, '23'], [1, ['2D', '3D']]]}
- {base: gpr, index: gpr, offset: ~, scale: 1, port_pressure: [[1, '23'], [1, ['2D', '3D']]]}
- {base: gpr, index: gpr, offset: ~, scale: 8, port_pressure: [[1, '23'], [1, ['2D', '3D']]]}
- {base: gpr, index: gpr, offset: imd, scale: 1, port_pressure: [[1, '23'], [1, ['2D', '3D']]]}
- {base: gpr, index: gpr, offset: imd, scale: 8, port_pressure: [[1, '23'], [1, ['2D', '3D']]]}
- {base: gpr, index: gpr, offset: id, scale: 1, port_pressure: [[1, '23'], [1, ['2D', '3D']]]}
- {base: gpr, index: gpr, offset: id, scale: 8, port_pressure: [[1, '23'], [1, ['2D', '3D']]]}
load_throughput_default: [[1, '23'], [1, ['2D', '3D']]]
ports: ['0', 0DV, '1', '2', 2D, '3', 3D, '4', '5', '6', '7']
port_model_scheme: |
┌------------------------------------------------------------------------┐

1
osaca/data/hsw.yml
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@@ -16,6 +16,7 @@ load_throughput:
- {base: gpr, index: ~, offset: imd, scale: 8, port_pressure: [[1, '23'], [1, [2D, 3D]]]}
- {base: gpr, index: ~, offset: ~, scale: 1, port_pressure: [[1, '23'], [1, [2D, 3D]]]}
- {base: gpr, index: ~, offset: ~, scale: 8, port_pressure: [[1, '23'], [1, [2D, 3D]]]}
load_throughput_default: [[1, '23'], [1, ['2D', '3D']]]
ports: ['0', 0DV, '1', '2', '2D', '3', '3D', '4', '5', '6', '7']
port_model_scheme: |
┌------------------------------------------------------------------------┐

1
osaca/data/ivb.yml
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@@ -16,6 +16,7 @@ load_throughput:
- {base: gpr, index: ~, offset: imd, scale: 8, port_pressure: [[1, '23'], [1, [2D, 3D]]]}
- {base: gpr, index: ~, offset: ~, scale: 1, port_pressure: [[1, '23'], [1, [2D, 3D]]]}
- {base: gpr, index: ~, offset: ~, scale: 8, port_pressure: [[1, '23'], [1, [2D, 3D]]]}
load_throughput_default: [[1, '23'], [1, ['2D', '3D']]]
ports: ['0', '0DV', '1', '2', '2D', '3', '3D', '4', '5']
port_model_scheme: |
┌-----------------------------------------------------┐

1
osaca/data/skx.yml
View File

@@ -16,6 +16,7 @@ load_throughput:
- {base: gpr, index: gpr, offset: ~, scale: 8, port_pressure: [[1, '23'], [1, ['2D', '3D']]]}
- {base: gpr, index: gpr, offset: imd, scale: 1, port_pressure: [[1, '23'], [1, ['2D', '3D']]]}
- {base: gpr, index: gpr, offset: imd, scale: 8, port_pressure: [[1, '23'], [1, ['2D', '3D']]]}
load_throughput_default: [[1, '23'], [1, ['2D', '3D']]]
ports: ['0', 0DV, '1', '2', 2D, '3', 3D, '4', '5', '6', '7']
port_model_scheme: |
┌------------------------------------------------------------------------┐

1
osaca/data/snb.yml
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@@ -16,6 +16,7 @@ load_throughput:
- {base: gpr, index: ~, offset: imd, scale: 8, port_pressure: [[1, '23'], [1, [2D, 3D]]]}
- {base: gpr, index: ~, offset: ~, scale: 1, port_pressure: [[1, '23'], [1, [2D, 3D]]]}
- {base: gpr, index: ~, offset: ~, scale: 8, port_pressure: [[1, '23'], [1, [2D, 3D]]]}
load_throughput_default: [[1, '23'], [1, ['2D', '3D']]]
ports: ['0', '0DV', '1', '2', '2D', '3', '3D', '4', '5']
port_model_scheme: |
┌-----------------------------------------------------┐

1
osaca/data/tx2.yml
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@@ -40,6 +40,7 @@ load_throughput:
- {base: x, index: x, offset: imd, scale: 8, pre-indexed: false, post-indexed: false, port_pressure: [[1, '34']]}
- {base: x, index: x, offset: imd, scale: 8, pre-indexed: true, post-indexed: true, port_pressure: [[1, '34']]}
- {base: x, index: x, offset: imd, scale: 8, pre-indexed: true, post-indexed: false, port_pressure: [[1, '34']]}
load_throughput_default: [[1, '34']]
ports: ['0', 0DV, '1', 1DV, '2', '3', '4', '5']
port_model_scheme: |
┌-----------------------------------------------------------┐

1
osaca/data/zen1.yml
View File

@@ -13,6 +13,7 @@ load_throughput:
- {base: gpr, index: gpr, offset: ~, scale: 8, port_pressure: [[1, '89'], [1, ['8D','9D']]]}
- {base: gpr, index: gpr, offset: imd, scale: 1, port_pressure: [[1, '89'], [1, ['8D','9D']]]}
- {base: gpr, index: gpr, offset: imd, scale: 8, port_pressure: [[1, '89'], [1, ['8D','9D']]]}
load_throughput_default: [[1, '89'], [1, ['8D', '9D']]]
hidden_loads: false
ports: ['0', '1', '2', '3', 3DV, '4', '5', '6', '7', '8', '9', 8D, 9D, ST]
port_model_scheme: |

2
osaca/frontend.py
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@@ -197,7 +197,7 @@ class Frontend(object):
sums[dep] = sum(
[instr_form['latency_lcd'] for instr_form in dep_dict[dep]['dependencies']]
)
lcd_sum = max(sums.values())
lcd_sum = max(sums.values()) if len(sums) > 0 else 0.0
lcd_lines = []
longest_lcd = [line_no for line_no in sums if sums[line_no] == lcd_sum][0]
lcd_lines = [d['line_number'] for d in dep_dict[longest_lcd]['dependencies']]

2
osaca/parser/parser_x86att.py
View File

@@ -21,12 +21,14 @@ class ParserX86ATT(BaseParser):
pp.ZeroOrMore(pp.Word(pp.printables))
).setResultsName(self.COMMENT_ID)
# Define x86 assembly identifier
relocation = pp.Combine(pp.Literal('@') + pp.Word(pp.alphas))
id_offset = pp.Word(pp.nums) + pp.Suppress(pp.Literal('+'))
first = pp.Word(pp.alphas + '_.', exact=1)
rest = pp.Word(pp.alphanums + '$_.')
identifier = pp.Group(
pp.Optional(id_offset).setResultsName('offset')
+ pp.Combine(first + pp.Optional(rest)).setResultsName('name')
+ pp.Optional(relocation).setResultsName('relocation')
).setResultsName('identifier')
# Label
self.label = pp.Group(

5
osaca/semantics/arch_semantics.py
View File

@@ -249,7 +249,10 @@ class ArchSemantics(ISASemantics):
def convert_mem_to_reg(self, memory, reg_type, reg_id='0'):
if self._isa == 'x86':
register = {'register': {'name': reg_type + reg_id}}
if reg_type == 'gpr':
register = {'register': {'name': 'r' + str(int(reg_id) + 9)}}
else:
register = {'register': {'name': reg_type + reg_id}}
elif self._isa == 'aarch64':
register = {'register': {'prefix': reg_type, 'name': reg_id}}
return register

7
osaca/semantics/hw_model.py
View File

@@ -155,7 +155,7 @@ class MachineModel(object):
ld_tp = [m for m in self._data['load_throughput'] if self._match_mem_entries(memory, m)]
if len(ld_tp) > 0:
return ld_tp[0]['port_pressure']
return None
return self._data['load_throughput_default']
def _match_mem_entries(self, mem, i_mem):
if self._data['isa'].lower() == 'aarch64':
@@ -490,6 +490,11 @@ class MachineModel(object):
or (i_mem['offset'] is None and mem['offset']['value'] == '0')
)
)
or (
mem['offset'] is not None
and 'identifier' in mem['offset']
and i_mem['offset'] == 'id'
)
)
# check index
and (