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https://github.com/RRZE-HPC/OSACA.git
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runnable pmbs version
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@@ -6,6 +6,7 @@ ROB_size: 180
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retired_uOps_per_cycle: 4
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retired_uOps_per_cycle: 4
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scheduler_size: 60
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scheduler_size: 60
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hidden_loads: false
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hidden_loads: false
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load_latency: {w: 4.0, x: 4.0, b: 4.0, h: 4.0, s: 4.0, d: 4.0, q: 4.0, v: 4.0}
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ports: ["0", "0DV", "1", "1DV", "2", "3", "4", "5"]
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ports: ["0", "0DV", "1", "1DV", "2", "3", "4", "5"]
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port_model_scheme: |
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port_model_scheme: |
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┌-----------------------------------------------------------┐
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┌-----------------------------------------------------------┐
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@@ -389,7 +390,7 @@ instruction_forms:
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pre-indexed: false
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pre-indexed: false
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post-indexed: false
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post-indexed: false
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throughput: 0.5
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throughput: 0.5
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latency: 4.0 # 0 0DV 1 1DV 2 3 4 5
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latency: 0.0 # 0 0DV 1 1DV 2 3 4 5
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port_pressure: [0.0, 0.0, 0.0, 0.0, 0.0, 0.5, 0.5, 0.0]
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port_pressure: [0.0, 0.0, 0.0, 0.0, 0.0, 0.5, 0.5, 0.0]
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- name: "ldr"
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- name: "ldr"
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operands:
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operands:
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@@ -403,7 +404,7 @@ instruction_forms:
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pre-indexed: false
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pre-indexed: false
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post-indexed: false
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post-indexed: false
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throughput: 0.5
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throughput: 0.5
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latency: 4.0 # 0 0DV 1 1DV 2 3 4 5
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latency: 0.0 # 0 0DV 1 1DV 2 3 4 5
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port_pressure: [0.0, 0.0, 0.0, 0.0, 0.0, 0.5, 0.5, 0.0]
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port_pressure: [0.0, 0.0, 0.0, 0.0, 0.0, 0.5, 0.5, 0.0]
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- name: "ldr"
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- name: "ldr"
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operands:
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operands:
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@@ -417,7 +418,7 @@ instruction_forms:
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pre-indexed: false
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pre-indexed: false
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post-indexed: false
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post-indexed: false
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throughput: 0.5
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throughput: 0.5
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latency: 4.0 # 0 0DV 1 1DV 2 3 4 5
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latency: 0.0 # 0 0DV 1 1DV 2 3 4 5
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port_pressure: [0.0, 0.0, 0.0, 0.0, 0.0, 0.5, 0.5, 0.0]
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port_pressure: [0.0, 0.0, 0.0, 0.0, 0.0, 0.5, 0.5, 0.0]
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- name: "ldr"
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- name: "ldr"
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operands:
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operands:
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@@ -431,7 +432,7 @@ instruction_forms:
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pre-indexed: false
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pre-indexed: false
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post-indexed: true
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post-indexed: true
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throughput: 0.5
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throughput: 0.5
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latency: 4.0 # 0 0DV 1 1DV 2 3 4 5
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latency: 0.0 # 0 0DV 1 1DV 2 3 4 5
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port_pressure: [0.0, 0.0, 0.0, 0.0, 0.0, 0.5, 0.5, 0.0]
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port_pressure: [0.0, 0.0, 0.0, 0.0, 0.0, 0.5, 0.5, 0.0]
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- name: "ldr"
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- name: "ldr"
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operands:
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operands:
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@@ -445,7 +446,7 @@ instruction_forms:
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pre-indexed: false
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pre-indexed: false
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post-indexed: false
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post-indexed: false
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throughput: 0.5
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throughput: 0.5
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latency: 4.0 # 0 0DV 1 1DV 2 3 4 5
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latency: 0.0 # 0 0DV 1 1DV 2 3 4 5
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port_pressure: [0.0, 0.0, 0.0, 0.0, 0.0, 0.5, 0.5, 0.0]
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port_pressure: [0.0, 0.0, 0.0, 0.0, 0.0, 0.5, 0.5, 0.0]
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- name: "ldr"
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- name: "ldr"
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operands:
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operands:
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@@ -459,7 +460,7 @@ instruction_forms:
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pre-indexed: false
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pre-indexed: false
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post-indexed: false
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post-indexed: false
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throughput: 0.5
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throughput: 0.5
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latency: 4.0 # 0 0DV 1 1DV 2 3 4 5
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latency: 0.0 # 0 0DV 1 1DV 2 3 4 5
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port_pressure: [0.0, 0.0, 0.0, 0.0, 0.0, 0.5, 0.5, 0.0]
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port_pressure: [0.0, 0.0, 0.0, 0.0, 0.0, 0.5, 0.5, 0.0]
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- name: "ldr"
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- name: "ldr"
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operands:
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operands:
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@@ -473,7 +474,7 @@ instruction_forms:
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pre-indexed: false
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pre-indexed: false
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post-indexed: false
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post-indexed: false
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throughput: 0.5
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throughput: 0.5
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latency: 4.0 # 0 0DV 1 1DV 2 3 4 5
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latency: 0.0 # 0 0DV 1 1DV 2 3 4 5
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port_pressure: [0.0, 0.0, 0.0, 0.0, 0.0, 0.5, 0.5, 0.0]
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port_pressure: [0.0, 0.0, 0.0, 0.0, 0.0, 0.5, 0.5, 0.0]
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- name: "mov"
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- name: "mov"
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operands:
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operands:
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@@ -16,10 +16,12 @@ class ParserX86ATT(BaseParser):
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pp.ZeroOrMore(pp.Word(pp.printables))
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pp.ZeroOrMore(pp.Word(pp.printables))
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).setResultsName(self.COMMENT_ID)
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).setResultsName(self.COMMENT_ID)
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# Define x86 assembly identifier
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# Define x86 assembly identifier
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id_offset = pp.Word(pp.nums) + pp.Suppress(pp.Literal('+'))
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first = pp.Word(pp.alphas + '_.', exact=1)
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first = pp.Word(pp.alphas + '_.', exact=1)
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rest = pp.Word(pp.alphanums + '_.')
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rest = pp.Word(pp.alphanums + '$_.')
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identifier = pp.Group(
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identifier = pp.Group(
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pp.Combine(first + pp.Optional(rest)).setResultsName('name')
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pp.Optional(id_offset).setResultsName('offset')
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+ pp.Combine(first + pp.Optional(rest)).setResultsName('name')
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).setResultsName('identifier')
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).setResultsName('identifier')
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# Label
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# Label
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self.label = pp.Group(
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self.label = pp.Group(
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@@ -16,9 +16,6 @@ class KernelDG(nx.DiGraph):
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self.model = hw_model
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self.model = hw_model
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self.dg = self.create_DG(self.kernel)
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self.dg = self.create_DG(self.kernel)
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self.loopcarried_deps = self.check_for_loopcarried_dep(self.kernel)
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self.loopcarried_deps = self.check_for_loopcarried_dep(self.kernel)
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import pdb
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pdb.set_trace()
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def create_DG(self, kernel):
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def create_DG(self, kernel):
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# 1. go through kernel instruction forms and add them as node attribute
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# 1. go through kernel instruction forms and add them as node attribute
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@@ -53,7 +50,7 @@ class KernelDG(nx.DiGraph):
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instruction_form['line_number'],
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instruction_form['line_number'],
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latency=load_lat,
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latency=load_lat,
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)
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)
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for dep in self.find_depending(instruction_form, kernel[i + 1 :]):
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for dep in self.find_depending(instruction_form, kernel[i + 1:]):
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dg.add_edge(
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dg.add_edge(
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instruction_form['line_number'],
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instruction_form['line_number'],
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dep['line_number'],
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dep['line_number'],
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