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Fix the x86 ISA description to indicate that the register of SAR and SAL is read/write.

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pleroy
2024-12-29 18:11:15 +01:00
parent b7e4acc905
commit 1eb82a6f0a
2 changed files with 6 additions and 1 deletions
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2
osaca/data/isa/x86.yml
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@@ -4415,7 +4415,7 @@ instruction_forms:
name: "xmm"
source: true
destination: true
- name: [shl, shr, shlq, shrq]
- name: [sal, sar, salq, sarq, shl, shr, shlq, shrq]
operands:
- class: "immediate"
imd: "int"

5
tests/test_semantics.py
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@@ -849,6 +849,9 @@ class TestSemanticTools(unittest.TestCase):
instr_form_r_ymm = self.parser_x86_intel.parse_line("vmovapd ymm0, ymm1")
self.semantics_csx_intel.normalize_instruction_form(instr_form_r_ymm)
self.semantics_csx_intel.assign_src_dst(instr_form_r_ymm)
instr_form_rw_sar = self.parser_x86_intel.parse_line("sar rcx, 43")
self.semantics_csx_intel.normalize_instruction_form(instr_form_rw_sar)
self.semantics_csx_intel.assign_src_dst(instr_form_rw_sar)
self.assertTrue(dag.is_read(reg_rcx, instr_form_r_c))
self.assertFalse(dag.is_read(reg_rcx, instr_form_non_r_c))
self.assertFalse(dag.is_read(reg_rcx, instr_form_w_c))
@@ -860,6 +863,8 @@ class TestSemanticTools(unittest.TestCase):
self.assertTrue(dag.is_written(reg_ymm1, instr_form_rw_ymm_1))
self.assertTrue(dag.is_written(reg_ymm1, instr_form_rw_ymm_2))
self.assertFalse(dag.is_written(reg_ymm1, instr_form_r_ymm))
self.assertTrue(dag.is_read(reg_rcx, instr_form_rw_sar))
self.assertTrue(dag.is_written(reg_rcx, instr_form_rw_sar))
def test_is_read_is_written_AArch64(self):
# independent form HW model