Fix the x86 ISA description to indicate that the register of SAR and SAL is read/write.

2025-12-16 09:00:05 +01:00 · 2024-12-29 18:11:15 +01:00
parent b7e4acc905
commit 1eb82a6f0a
2 changed files with 6 additions and 1 deletions
--- a/osaca/data/isa/x86.yml
+++ b/osaca/data/isa/x86.yml
@@ -4415,7 +4415,7 @@ instruction_forms:
          name: "xmm"
          source: true
          destination: true
-    - name: [shl, shr, shlq, shrq]
+    - name: [sal, sar, salq, sarq, shl, shr, shlq, shrq]
      operands:
        - class: "immediate"
          imd: "int"