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https://github.com/RRZE-HPC/OSACA.git
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enhancements for SVE support
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JanLJL
@@ -91,31 +91,49 @@ class ParserAArch64(BaseParser):
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^ pp.CaselessLiteral('ror')
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^ pp.CaselessLiteral('sxtw')
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^ pp.CaselessLiteral('uxtw')
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^ pp.CaselessLiteral('mul vl')
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)
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arith_immediate = pp.Group(
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immediate.setResultsName('base_immediate')
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+ pp.Suppress(pp.Literal(','))
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+ shift_op.setResultsName('shift_op')
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+ immediate.setResultsName('shift')
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+ pp.Optional(immediate).setResultsName('shift')
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).setResultsName(self.IMMEDIATE_ID)
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# Register:
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# scalar: [XWBHSDQ][0-9]{1,2} | vector: V[0-9]{1,2}\.[12468]{1,2}[BHSD]()?
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# define SP and ZR register aliases as regex, due to pyparsing does not support
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# scalar: [XWBHSDQ][0-9]{1,2} | vector: [VZ][0-9]{1,2}(\.[12468]{1,2}[BHSD])?
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# | predicate: P[0-9]{1,2}(/[ZM])?
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# ignore vector len control ZCR_EL[123] for now
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# define SP, ZR register aliases as regex, due to pyparsing does not support
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# proper lookahead
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alias_r31_sp = pp.Regex('(?P<prefix>[a-zA-Z])?(?P<name>(sp|SP))')
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alias_r31_zr = pp.Regex('(?P<prefix>[a-zA-Z])?(?P<name>(zr|ZR))')
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scalar = pp.Word(pp.alphas, exact=1).setResultsName('prefix') + pp.Word(
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scalar = pp.Word('xwbhsdqXWBHSDQ', exact=1).setResultsName('prefix') + pp.Word(
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pp.nums
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).setResultsName('name')
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index = pp.Literal('[') + pp.Word(pp.nums).setResultsName('index') + pp.Literal(']')
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vector = (
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pp.CaselessLiteral('v').setResultsName('prefix')
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pp.oneOf('v z', caseless=True).setResultsName('prefix')
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+ pp.Word(pp.nums).setResultsName('name')
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+ pp.Literal('.')
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+ pp.Optional(pp.Word('12468')).setResultsName('lanes')
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+ pp.Word(pp.alphas, exact=1).setResultsName('shape')
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+ pp.Optional(index)
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)
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predicate = (
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pp.CaselessLiteral('p').setResultsName('prefix')
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+ pp.Word(pp.nums).setResultsName('name')
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+ pp.Optional(
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(
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pp.Suppress(pp.Literal('/'))
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+ pp.oneOf('z m', caseless=True).setResultsName('predication')
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)
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| (
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pp.Literal('.')
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+ pp.Optional(pp.Word('12468')).setResultsName('lanes')
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+ pp.Word(pp.alphas, exact=1).setResultsName('shape')
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)
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)
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)
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self.list_element = vector ^ scalar
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register_list = (
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pp.Literal('{')
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@@ -129,7 +147,8 @@ class ParserAArch64(BaseParser):
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+ pp.Optional(index)
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)
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register = pp.Group(
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(alias_r31_sp | alias_r31_zr | vector | scalar | register_list)
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(alias_r31_sp | alias_r31_zr | vector | scalar | predicate | register_list)
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#(alias_r31_sp | alias_r31_zr | vector | scalar | predicate | register_list)
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+ pp.Optional(
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pp.Suppress(pp.Literal(','))
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+ shift_op.setResultsName('shift_op')
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@@ -144,7 +163,7 @@ class ParserAArch64(BaseParser):
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pp.Literal('[')
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+ pp.Optional(register.setResultsName('base'))
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+ pp.Optional(pp.Suppress(pp.Literal(',')))
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+ pp.Optional(register_index ^ immediate.setResultsName('offset'))
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+ pp.Optional(register_index ^ (immediate ^ arith_immediate).setResultsName('offset'))
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+ pp.Literal(']')
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+ pp.Optional(
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pp.Literal('!').setResultsName('pre_indexed')
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@@ -177,6 +196,11 @@ class ParserAArch64(BaseParser):
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+ pp.Optional(self.comment)
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)
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# for testing
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self.predicate = predicate
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self.vector = vector
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self.register = register
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def parse_line(self, line, line_number=None):
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"""
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Parse line and return instruction form.
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@@ -193,7 +217,7 @@ class ParserAArch64(BaseParser):
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self.DIRECTIVE_ID: None,
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self.COMMENT_ID: None,
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self.LABEL_ID: None,
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'line': line.strip(),
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'line': line.strip().replace('\t',' '),
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'line_number': line_number,
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}
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)
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@@ -351,18 +375,20 @@ class ParserAArch64(BaseParser):
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def process_register_list(self, register_list):
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"""Post-process register lists (e.g., {r0,r3,r5}) and register ranges (e.g., {r0-r7})"""
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# Remove unnecessarily created dictionary entries during parsing
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vlist = []
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rlist = []
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dict_name = ''
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if 'list' in register_list:
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dict_name = 'list'
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if 'range' in register_list:
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dict_name = 'range'
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for v in register_list[dict_name]:
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vlist.append(
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AttrDict.convert_dict(self.list_element.parseString(v, parseAll=True).asDict())
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for r in register_list[dict_name]:
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rlist.append(
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AttrDict.convert_dict(self.list_element.parseString(r, parseAll=True).asDict())
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)
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index = None if 'index' not in register_list else register_list['index']
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new_dict = AttrDict({dict_name: vlist, 'index': index})
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new_dict = AttrDict({dict_name: rlist, 'index': index})
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if len(new_dict[dict_name]) == 1:
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return AttrDict({self.REGISTER_ID: new_dict[dict_name][0]})
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return AttrDict({self.REGISTER_ID: new_dict})
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def process_immediate(self, immediate):
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@@ -440,7 +466,7 @@ class ParserAArch64(BaseParser):
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def is_vector_register(self, register):
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"""Check if register is a vector register"""
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if register['prefix'] in 'bhsdqv':
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if register['prefix'] in 'bhsdqvz':
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return True
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return False
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@@ -455,7 +481,7 @@ class ParserAArch64(BaseParser):
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def is_reg_dependend_of(self, reg_a, reg_b):
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"""Check if ``reg_a`` is dependent on ``reg_b``"""
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prefixes_gpr = 'wx'
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prefixes_vec = 'bhsdqv'
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prefixes_vec = 'bhsdqvz'
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if reg_a['name'] == reg_b['name']:
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if reg_a['prefix'].lower() in prefixes_gpr and reg_b['prefix'].lower() in prefixes_gpr:
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return True
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