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Merge branch 'pr84' into feature/tsv110

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Qingcai Jiang
2022-02-18 16:04:55 +08:00
parent c2787babee a447e289ff
commit 2eb6023b7a
2 changed files with 373 additions and 599 deletions
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966
osaca/data/tsv110.yml
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6
osaca/semantics/hw_model.py
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@@ -639,6 +639,12 @@ class MachineModel(object):
):
return True
return False
if "lanes" in reg:
if "lanes" in i_reg and (
reg["lanes"] == i_reg["lanes"] or self.WILDCARD in (reg["lanes"] + i_reg["lanes"])
):
return True
return False
return True
def _is_x86_reg_type(self, i_reg, reg, consider_masking=False):