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more tests for Arm

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This commit is contained in:
JanLJL
2019-08-09 11:01:08 +02:00
parent 1b9faa4df5
commit 36bc184f4d
4 changed files with 54 additions and 11 deletions
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13
osaca/frontend.py
View File

@@ -2,11 +2,10 @@
import os
import re
from functools import reduce
from ruamel import yaml
from osaca.semantics import INSTR_FLAGS
from osaca.semantics import INSTR_FLAGS, SemanticsAppender
class Frontend(object):
@@ -67,17 +66,9 @@ class Frontend(object):
continue
print(line)
print()
tp_sum = self._get_throughput_sum(kernel)
tp_sum = SemanticsAppender.get_throughput_sum(kernel)
print(lineno_filler + self._get_port_pressure(tp_sum, port_len, ' '))
def _get_throughput_sum(self, kernel):
tp_sum = reduce(
(lambda x, y: [sum(z) for z in zip(x, y)]),
[instr['port_pressure'] for instr in kernel],
)
tp_sum = [round(x, 2) for x in tp_sum]
return tp_sum
def _get_separator_list(self, separator, separator_2=' '):
separator_list = []
for i in range(len(self._data['ports']) - 1):

3
osaca/semantics/hw_model.py
View File

@@ -66,6 +66,9 @@ class MachineModel(object):
def get_ISA(self):
return self._data['isa']
def get_arch(self):
return self._data['arch_code']
######################################################
def _match_operands(self, i_operands, operands):

10
osaca/semantics/semanticsAppender.py
View File

@@ -2,6 +2,7 @@
import os
import warnings
from functools import reduce
from osaca.parser import AttrDict
@@ -158,3 +159,12 @@ class SemanticsAppender(object):
def _get_regular_destination_AArch64(self, instruction_form):
# return first operand
return instruction_form['operands'][:1]
@staticmethod
def get_throughput_sum(kernel):
tp_sum = reduce(
(lambda x, y: [sum(z) for z in zip(x, y)]),
[instr['port_pressure'] for instr in kernel],
)
tp_sum = [round(x, 2) for x in tp_sum]
return tp_sum

39
tests/test_parser_AArch64v81.py
View File

@@ -78,6 +78,7 @@ class TestParserAArch64v81(unittest.TestCase):
instr4 = 'str x28, [sp, x1, lsl #4] //12.9'
instr5 = 'ldr x0, [x0, #:got_lo12:q2c]'
instr6 = 'adrp x0, :got:visited'
instr7 = 'fadd v17.2d, v16.2d, v1.2d'
parsed_1 = self.parser.parse_instruction(instr1)
parsed_2 = self.parser.parse_instruction(instr2)
@@ -85,6 +86,7 @@ class TestParserAArch64v81(unittest.TestCase):
parsed_4 = self.parser.parse_instruction(instr4)
parsed_5 = self.parser.parse_instruction(instr5)
parsed_6 = self.parser.parse_instruction(instr6)
parsed_7 = self.parser.parse_instruction(instr7)
self.assertEqual(parsed_1.instruction, 'vcvt.F32.S32')
self.assertEqual(parsed_1.operands[0].register.name, '1')
@@ -131,6 +133,13 @@ class TestParserAArch64v81(unittest.TestCase):
self.assertEqual(parsed_6.operands[1].identifier.relocation, ':got:')
self.assertEqual(parsed_6.operands[1].identifier.name, 'visited')
self.assertEqual(parsed_7.instruction, 'fadd')
self.assertEqual(parsed_7.operands[0].register.name, '17')
self.assertEqual(parsed_7.operands[0].register.prefix, 'v')
self.assertEqual(parsed_7.operands[0].register.lanes, '2')
self.assertEqual(parsed_7.operands[0].register.shape, 'd')
self.assertEqual(self.parser.get_full_reg_name(parsed_7.operands[2].register), 'v1.2d')
def test_parse_line(self):
line_comment = '// -- Begin main'
line_label = '.LBB0_1: // =>This Inner Loop Header: Depth=1'
@@ -283,6 +292,7 @@ class TestParserAArch64v81(unittest.TestCase):
imd_float_12 = {'float': {'mantissa': '790.0', 'e_sign': '-', 'exponent': '1'}}
imd_double_11 = {'double': {'mantissa': '0.79', 'e_sign': '+', 'exponent': '2'}}
imd_double_12 = {'double': {'mantissa': '790.0', 'e_sign': '-', 'exponent': '1'}}
identifier = {'identifier': {'name': '..B1.4'}}
value1 = self.parser.normalize_imd(imd_decimal_1)
self.assertEqual(value1, self.parser.normalize_imd(imd_hex_1))
@@ -293,6 +303,35 @@ class TestParserAArch64v81(unittest.TestCase):
self.assertEqual(self.parser.normalize_imd(imd_float_12), value1)
self.assertEqual(self.parser.normalize_imd(imd_double_11), value1)
self.assertEqual(self.parser.normalize_imd(imd_double_12), value1)
self.assertEqual(self.parser.normalize_imd(identifier), identifier)
def test_multiple_regs(self):
instr_range = 'PUSH {r5-r7}'
reg_range = AttrDict({
'register': {
'range': [
{'prefix': 'r', 'name': '5'},
{'prefix': 'r', 'name': '7'}
],
'index': None
}
})
instr_list = 'POP {r5, r7, r9}'
reg_list = AttrDict({
'register': {
'list': [
{'prefix': 'r', 'name': '5'},
{'prefix': 'r', 'name': '7'},
{'prefix': 'r', 'name': '9'}
],
'index': None
}
})
prange = self.parser.parse_line(instr_range)
plist = self.parser.parse_line(instr_list)
self.assertEqual(prange.operands[0], reg_range)
self.assertEqual(plist.operands[0], reg_list)
def test_reg_dependency(self):
reg_1_1 = AttrDict({'prefix': 'b', 'name': '1'})