new instructions

osaca/data/a64fx.yml

@@ -407,6 +407,50 @@ instruction_forms:
   throughput: 29.0
   latency: 29.0  # 	1*p0+29*p0DV
   port_pressure: [[1, '0'], [29.0, [0DV]]]
+- name: fcmla
+  operands:
+  - class: register
+    prefix: z
+    shape: d
+    width: '*'
+  - class: register
+    prefix: p
+    predication: '*'
+  - class: register
+    prefix: z
+    shape: d
+    width: '*'
+  - class: register
+    prefix: z
+    shape: d
+    width: '*'
+  - class: immediate
+    imd: int
+  throughput: 2.0
+  latency: 16.0  # 	2*p0+1*p02
+  port_pressure: [[2, '0'], [1, '02']]
+- name: fcadd
+  operands:
+  - class: register
+    prefix: z
+    shape: d
+    width: '*'
+  - class: register
+    prefix: p
+    predication: '*'
+  - class: register
+    prefix: z
+    shape: d
+    width: '*'
+  - class: register
+    prefix: z
+    shape: d
+    width: '*'
+  - class: immediate
+    imd: int
+  throughput: 1.0
+  latency: 15.0  # 	1*p0+1*p2
+  port_pressure: [[1, '0'], [1, '2']]
 - name: fdiv
   operands:
   - class: register
@@ -581,6 +625,43 @@ instruction_forms:
   throughput: 0.5
   latency: 4.0  # 	1*p02
   port_pressure: [[1, '02']]
+- name: fsub
+  operands:
+  - class: register
+    prefix: z
+    shape: d
+    width: '*'
+  - class: register
+    prefix: p
+  - class: register
+    prefix: z
+    shape: d
+    width: '*'
+  - class: register
+    prefix: z
+    shape: d
+    width: '*'
+  throughput: 0.5
+  latency: 9.0  # 	1*p02
+  port_pressure: [[1, '02']]
+- name: fsub
+  operands:
+  - class: register
+    prefix: z
+    shape: d
+    width: '*'
+  - class: register
+    prefix: z
+    shape: d
+    width: '*'
+  - class: register
+    prefix: z
+    shape: d
+    width: '*'
+  throughput: 0.5
+  latency: 9.0  # 	1*p02
+  port_pressure: [[1, '02']]
+
 - name: fsub
   operands:
   - class: register
@@ -615,13 +696,24 @@ instruction_forms:
   throughput: 0.5
   latency: 9.0  # 	1*p02
   port_pressure: [[1, '02']]
-- name: incd
+- name: [incb, incd]
   operands:
   - class: register
     prefix: x
   throughput: 0.5
   latency: 1.0  # 	1*p34
   port_pressure: [[1, '34']]
+- name: [incb, incd]
+  operands:
+  - class: register
+    prefix: x
+  - class: identifier
+  - class: identifier
+  - class: immediate
+    imd: int
+  throughput: 0.5
+  latency: 1.0  # 	1*p34
+  port_pressure: [[1, '34']]
 - name: ld1d
   operands:
   - class: register
@@ -634,7 +726,7 @@ instruction_forms:
     base: x
     offset: ~
     index: ~
-    scale: ~
+    scale: '*'
     pre-indexed: false
     post-indexed: false
   throughput: 0.5
@@ -679,14 +771,14 @@ instruction_forms:
 - name: ldp
   operands:
   - class: register
-    prefix: d
+    prefix: x
   - class: register
-    prefix: d
+    prefix: x
   - class: memory
     base: x
-    offset: imd
-    index: ~
-    scale: 1
+    offset: '*'
+    index: '*'
+    scale: '*'
     pre-indexed: false
     post-indexed: false
   throughput: 1.0
@@ -695,14 +787,14 @@ instruction_forms:
 - name: ldp
   operands:
   - class: register
-    prefix: d
+    prefix: x
   - class: register
-    prefix: d
+    prefix: x
   - class: memory
     base: x
-    offset: imd
-    index: ~
-    scale: 1
+    offset: '*'
+    index: '*'
+    scale: '*'
     pre-indexed: false
     post-indexed: true
   throughput: 1.0
@@ -711,19 +803,67 @@ instruction_forms:
 - name: ldp
   operands:
   - class: register
-    prefix: q
+    prefix: x
   - class: register
-    prefix: q
+    prefix: x
   - class: memory
     base: x
     offset: '*'
     index: '*'
-    scale: 1
+    scale: '*'
+    pre-indexed: false
+    post-indexed: true
+  throughput: 1.0
+  latency: 8.0  # 	2*p56+2*p5D6D+1*p0234
+  port_pressure: [[2, '56'], [2, ['5D', '6D']], [1, '0234']]
+- name: ldp
+  operands:
+  - class: register
+    prefix: d
+  - class: register
+    prefix: d
+  - class: memory
+    base: x
+    offset: '*'
+    index: '*'
+    scale: '*'
     pre-indexed: false
     post-indexed: false
   throughput: 1.0
   latency: 8.0  # 	2*p56+2*p5D6D
   port_pressure: [[2, '56'], [2, ['5D', '6D']]]
+- name: ldp
+  operands:
+  - class: register
+    prefix: d
+  - class: register
+    prefix: d
+  - class: memory
+    base: x
+    offset: '*'
+    index: '*'
+    scale: '*'
+    pre-indexed: false
+    post-indexed: true
+  throughput: 1.0
+  latency: 8.0  # 	2*p56+2*p5D6D+1*p0234
+  port_pressure: [[2, '56'], [2, ['5D', '6D']], [1, '0234']]
+- name: ldp
+  operands:
+  - class: register
+    prefix: d
+  - class: register
+    prefix: d
+  - class: memory
+    base: x
+    offset: '*'
+    index: '*'
+    scale: '*'
+    pre-indexed: false
+    post-indexed: true
+  throughput: 1.0
+  latency: 8.0  # 	2*p56+2*p5D6D+1*p0234
+  port_pressure: [[2, '56'], [2, ['5D', '6D']], [1, '0234']]
 - name: ldp
   operands:
   - class: register
@@ -772,22 +912,6 @@ instruction_forms:
   throughput: 1.0
   latency: 8.0  # 	2*p56+2*p5D6D+1*p0234
   port_pressure: [[2, '56'], [2, ['5D', '6D']], [1, '0234']]
-- name: ldp
-  operands:
-  - class: register
-    prefix: d
-  - class: register
-    prefix: d
-  - class: memory
-    base: x
-    offset: '*'
-    index: '*'
-    scale: '*'
-    pre-indexed: false
-    post-indexed: true
-  throughput: 1.0
-  latency: 8.0  # 	2*p56+2*p5D6D+1*p0234
-  port_pressure: [[2, '56'], [2, ['5D', '6D']], [1, '0234']]
 - name: ldur    # JL: assumed from ldr
   operands:
   - class: register
@@ -802,6 +926,20 @@ instruction_forms:
   throughput: 0.5
   latency: 5.0  # 	1*p56+1*p5D6D
   port_pressure: [[1, '56'], [1, ['5D', '6D']]]
+- name: ldr     # JL: assumed from manual
+  operands:
+  - class: register
+    prefix: z
+  - class: memory
+    base: x
+    offset: '*'
+    index: '*'
+    scale: '*'
+    post-indexed: false
+    pre-indexed: false
+  throughput: 1.0
+  latency: 11.0  # 	1*p5+1*p5D
+  port_pressure: [[1, '5'], [1, ['5D',]]]
 - name: ldr
   operands:
   - class: register
@@ -828,26 +966,12 @@ instruction_forms:
     post-indexed: false
     pre-indexed: false
   throughput: 0.5
-  latency: 5.0  # 	1*p56+1*p5D6D
+  latency: 5.0  # 	2*p56+2*p5D6D
   port_pressure: [[1, '56'], [1, ['5D', '6D']]]
-- name: ldr
+- name: ldrb
   operands:
   - class: register
-    prefix: d
-  - class: memory
-    base: x
-    offset: imd
-    index: '*'
-    scale: '*'
-    post-indexed: false
-    pre-indexed: false
-  throughput: 0.5
-  latency: 5.0  # 	1*p56+1*p5D6D
-  port_pressure: [[1, '56'], [1, ['5D', '6D']]]
-- name: ldr
-  operands:
-  - class: register
-    prefix: d
+    prefix: w
   - class: memory
     base: x
     offset: '*'
@@ -976,6 +1100,17 @@ instruction_forms:
   throughput: 0.5
   latency: 4.0  # 	1*p02
   port_pressure: [[1, '02']]
+- name: movprfx
+  operands:
+  - class: register
+    prefix: z
+    shape: '*'
+  - class: register
+    prefix: z
+    shape: '*'
+  throughput: 0.5
+  latency: 4.0  # 	1*p02
+  port_pressure: [[1, '02']]
 - name: mul
   operands:
   - class: register
@@ -998,11 +1133,58 @@ instruction_forms:
   throughput: 1.0
   latency: 5.0  # 	1*p3
   port_pressure: [[1, '3']]
+- name: prfm
+  operands:
+  - class: prfop
+    type: '*'
+    target: '*'
+    policy: '*'
+  - class: memory
+    base: x
+    offset: '*'
+    index: '*'
+    scale: '*'
+    pre-indexed: false
+    post-indexed: false
+  throughput: 0.0
+  latency: 0
+  port_pressure: []
+- name: prfd
+  operands:
+  - class: prfop
+    type: '*'
+    target: '*'
+    policy: '*'
+  - class: register
+    prefix: p
+  - class: memory
+    base: x
+    offset: '*'
+    index: '*'
+    scale: '*'
+    pre-indexed: false
+    post-indexed: false
+  throughput: 0.0
+  latency: 0
+  port_pressure: []
 - name: ret
   operands: []
   throughput: 0.5
   latency: ~  #     1*p56
   port_pressure: [[1, '56']]
+- name: smaddl
+  operands:
+  - class: register
+    prefix: x
+  - class: register
+    prefix: w
+  - class: register
+    prefix: w
+  - class: register
+    prefix: x
+  throughput: 2.0
+  latency: 6.0  # 	2*p3
+  port_pressure: [[2, '3']]
 - name: stp
   operands:
   - class: register
@@ -1241,6 +1423,20 @@ instruction_forms:
   throughput: 1.0
   latency: 0  # 	1*p56+1*p3+1*p0234
   port_pressure: [[1, '56'], [1, '3'], [1, '0234']]
+- name: str
+  operands:
+  - class: register
+    prefix: z
+  - class: memory
+    base: x
+    offset: '*'
+    index: '*'
+    scale: '*'
+    pre-indexed: false
+    post-indexed: false
+  throughput: 1.0
+  latency: 0  # 	1*p5+1*p6+1*p0
+  port_pressure: [[1, '5'], [1, '6'], [1, '0']]
 - name: st1d
   operands:
   - class: register
@@ -1324,6 +1520,32 @@ instruction_forms:
   throughput: 0.5
   latency: 1.0  # 	1*p34
   port_pressure: [[1, '34']]
+- name: sxtw
+  operands:
+  - class: register
+    prefix: x
+  - class: register
+    prefix: w
+  throughput: 0.5
+  latency: 1.0  # 	1*p34
+  port_pressure: [[1, '34']]
+- name: tbl
+  operands:
+  - class: register
+    prefix: z
+    shape: d
+    width: '*'
+  - class: register
+    prefix: z
+    shape: d
+    width: '*'
+  - class: register
+    prefix: z
+    shape: d
+    width: '*'
+  throughput: 1.0
+  latency: 6.0  # 	1*p0
+  port_pressure: [[1, '0']]
 - name: [whilele, whilelo, whilels, whilelt]
   operands:
   - class: register

osaca/data/isa/aarch64.yml

@@ -5,34 +5,62 @@ isa: "AArch64"
 #   mnemonic op1 ... opN
 # means that op1 is the only destination operand and op2 to op(N) are source operands.
 instruction_forms:
+    - name: [incb, incd]
+      operands:
+      - class: register
+        prefix: x
+        source: true
+        destination: true
+      throughput: 0.5
+      latency: 1.0  # 	1*p34
+      port_pressure: [[1, '34']]
+    - name: [incb, incd]
+      operands:
+      - class: register
+        prefix: x
+        source: true
+        destination: true
+      - class: identifier
+        source: false 
+        destination: false
+      - class: identifier
+        source: false 
+        destination: false
+      - class: immediate
+        imd: int
+        source: false 
+        destination: false
+      throughput: 0.5
+      latency: 1.0  # 	1*p34
+      port_pressure: [[1, '34']]
     - name: fmla
       operands:
-        - class: "register"
+        - class: register
           prefix: "*"
           shape: "*"
           source: true
           destination: true
-        - class: "register"
+        - class: register
           prefix: "*"
           shape: "*"
           source: true
           destination: false
-        - class: "register"
+        - class: register
           prefix: "*"
           shape: "*"
           source: true
           destination: false
     - name: ldp
       operands:
-        - class: "register"
+        - class: register
           prefix: "*"
           source: false
           destination: true
-        - class: "register"
+        - class: register
           prefix: "*"
           source: false
           destination: true
-        - class: "memory"
+        - class: memory
           base: "*"
           offset: "*"
           index: "*"
@@ -43,11 +71,11 @@ instruction_forms:
           destination: false
     - name: [ldr, ldur]
       operands:
-        - class: "register"
+        - class: register
           prefix: "*"
           source: false
           destination: true
-        - class: "memory"
+        - class: memory
           base: "*"
           offset: "*"
           index: "*"
@@ -58,15 +86,15 @@ instruction_forms:
           destination: false
     - name: stp
       operands:
-        - class: "register"
+        - class: register
           prefix: "*"
           source: true
           destination: false
-        - class: "register"
+        - class: register
           prefix: "*"
           source: true
           destination: false
-        - class: "memory"
+        - class: memory
           base: "*"
           offset: "*"
           index: "*"
@@ -77,11 +105,11 @@ instruction_forms:
           destination: true
     - name: [str, stur]
       operands:
-        - class: "register"
+        - class: register
           prefix: "*"
           source: true
           destination: false
-        - class: "memory"
+        - class: memory
           base: "*"
           offset: "*"
           index: "*"
@@ -92,71 +120,71 @@ instruction_forms:
           destination: true
     - name: cmp
       operands:
-        - class: "register"
+        - class: register
           prefix: "*"
           source: true
           destination: false
-        - class: "register"
+        - class: register
           prefix: "*"
           source: true
           destination: false
     - name: cmp
       operands:
-        - class: "register"
+        - class: register
           prefix: "*"
           source: true
           destination: false
-        - class: "immediate"
+        - class: immediate
           imd: "int"
           source: true
           destination: false
     - name: cmn
       operands:
-        - class: "register"
+        - class: register
           prefix: "*"
           source: true
           destination: false
-        - class: "register"
+        - class: register
           prefix: "*"
           source: true
           destination: false
     - name: cmn
       operands:
-        - class: "register"
+        - class: register
           prefix: "*"
           source: true
           destination: false
-        - class: "immediate"
+        - class: immediate
           imd: "int"
           source: true
           destination: false
     - name: fcmp
       operands:
-        - class: "register"
+        - class: register
           prefix: "*"
           source: true
           destination: false
-        - class: "register"
+        - class: register
           prefix: "*"
           source: true
           destination: false
     - name: fcmp
       operands:
-        - class: "register"
+        - class: register
           prefix: "*"
           source: true
           destination: false
-        - class: "immediate"
-          imd: "double"
+        - class: immediate
+          imd: double
           source: true
           destination: false
     - name: fcmp
       operands:
-        - class: "register"
+        - class: register
           prefix: "*"
           source: true
           destination: false
-        - class: "immediate"
-          imd: "float"
+        - class: immediate
+          imd: float
           source: true
           destination: false