remove dependency on MachineModel

This commit is contained in:
JanLJL
2025-03-04 17:42:52 +01:00
parent d772522400
commit 379e422290
3 changed files with 6 additions and 9 deletions

View File

@@ -13,7 +13,6 @@ from osaca.parser.identifier import IdentifierOperand
from osaca.parser.immediate import ImmediateOperand
from osaca.parser.condition import ConditionOperand
from osaca.parser.prefetch import PrefetchOperand
from osaca.semantics.hw_model import MachineModel
class ParserAArch64(BaseParser):
@@ -56,8 +55,8 @@ class ParserAArch64(BaseParser):
def normalize_instruction_form(
self,
instruction_form,
isa_model: MachineModel,
arch_model: MachineModel
isa_model,
arch_model
):
"""
If the instruction doesn't exist in the machine model, normalize it by dropping the shape

View File

@@ -13,7 +13,6 @@ from osaca.parser.label import LabelOperand
from osaca.parser.register import RegisterOperand
from osaca.parser.identifier import IdentifierOperand
from osaca.parser.immediate import ImmediateOperand
from osaca.semantics.hw_model import MachineModel
class ParserX86ATT(ParserX86):
@@ -66,8 +65,8 @@ class ParserX86ATT(ParserX86):
def normalize_instruction_form(
self,
instruction_form,
isa_model: MachineModel,
arch_model: MachineModel
isa_model,
arch_model
):
"""
If the instruction doesn't exist in the machine model, normalize it by dropping the GAS

View File

@@ -13,7 +13,6 @@ from osaca.parser.instruction_form import InstructionForm
from osaca.parser.label import LabelOperand
from osaca.parser.memory import MemoryOperand
from osaca.parser.register import RegisterOperand
from osaca.semantics.hw_model import MachineModel
# We assume any non-ASCII characters except control characters and line terminators can be part of
# identifiers; this is based on the assumption that no assembler uses non-ASCII white space and
@@ -78,8 +77,8 @@ class ParserX86Intel(ParserX86):
def normalize_instruction_form(
self,
instruction_form,
isa_model: MachineModel,
arch_model: MachineModel
isa_model,
arch_model
):
"""
If the model indicates that this instruction has a single destination that is the last