removed old testcases

This commit is contained in:
Jan Laukemann
2017-07-22 18:32:21 +02:00
parent ea0a4e6cb3
commit 42f5eab726
62 changed files with 0 additions and 5094 deletions

View File

@@ -1,100 +0,0 @@
#define INSTR add
#define NINST 24
#define N edi
#define i r8d
.intel_syntax noprefix
.globl ninst
.data
ninst:
.long NINST
.text
.globl latency
.type latency, @function
.align 32
latency:
push rbp
mov rbp, rsp
xor i, i
test N, N
jle done
# create DP 1.0
vpcmpeqw xmm0, xmm0, xmm0 # all ones
vpsllq xmm0, xmm0, 54 # logical left shift: 11111110..0 (54=64-(10-1))
vpsrlq xmm0, xmm0, 2 # logical right shift: 1 bit for sign; leading mantissa bit is zero
push rax
push rbx
push rcx
push rdx
push r9
push r10
push r11
push r12
push r13
push r14
push r15
xor rax, rax
xor rbx, rbx
xor rcx, rcx
xor rdx, rdx
xor r9, r9
xor r10, r10
xor r11, r11
xor r12, r12
xor r13, r13
xor r14, r14
xor r15, r15
# copy DP 1.0
vmovq rax, xmm0
vmovq rbx, xmm0
# Create DP 2.0
add rbx, rax
# Create DP 0.5
div rax
movq rcx, rax
vmovq rax, xmm0
loop:
inc i
INSTR edx, eax
INSTR r9d, ebx
INSTR r10d, ecx
INSTR edx, eax
INSTR r9d, ebx
INSTR r10d, ecx
INSTR r11d, eax
INSTR r12d, ebx
INSTR r13d, ecx
INSTR r14d, eax
INSTR r15d, ebx
INSTR eax, ecx
INSTR ebx, eax
INSTR ecx, ebx
INSTR edx, ecx
INSTR r9d, eax
INSTR r10d, ebx
INSTR r11d, ecx
INSTR r12d, eax
INSTR r13d, ebx
INSTR r14d, ecx
INSTR r15d, eax
INSTR eax, ebx
INSTR ebx, ecx
cmp i, N
jl loop
pop r15
pop r14
pop r13
pop r12
pop r11
pop r10
pop r9
pop rdx
pop rcx
pop rbx
pop rax
done:
mov rsp, rbp
pop rbp
ret
.size latency, .-latency

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@@ -1,100 +0,0 @@
#define INSTR add
#define NINST 24
#define N edi
#define i r8d
.intel_syntax noprefix
.globl ninst
.data
ninst:
.long NINST
.text
.globl latency
.type latency, @function
.align 32
latency:
push rbp
mov rbp, rsp
xor i, i
test N, N
jle done
# create DP 1.0
vpcmpeqw xmm0, xmm0, xmm0 # all ones
vpsllq xmm0, xmm0, 54 # logical left shift: 11111110..0 (54=64-(10-1))
vpsrlq xmm0, xmm0, 2 # logical right shift: 1 bit for sign; leading mantissa bit is zero
push rax
push rbx
push rcx
push rdx
push r9
push r10
push r11
push r12
push r13
push r14
push r15
xor rax, rax
xor rbx, rbx
xor rcx, rcx
xor rdx, rdx
xor r9, r9
xor r10, r10
xor r11, r11
xor r12, r12
xor r13, r13
xor r14, r14
xor r15, r15
# copy DP 1.0
vmovq rax, xmm0
vmovq rbx, xmm0
# Create DP 2.0
add rbx, rax
# Create DP 0.5
div rax
movq rcx, rax
vmovq rax, xmm0
loop:
inc i
INSTR eax, ebx
INSTR ebx, eax
INSTR eax, ebx
INSTR ebx, eax
INSTR eax, ebx
INSTR ebx, eax
INSTR eax, ebx
INSTR ebx, eax
INSTR eax, ebx
INSTR ebx, eax
INSTR eax, ebx
INSTR ebx, eax
INSTR eax, ebx
INSTR ebx, eax
INSTR eax, ebx
INSTR ebx, eax
INSTR eax, ebx
INSTR ebx, eax
INSTR eax, ebx
INSTR ebx, eax
INSTR eax, ebx
INSTR ebx, eax
INSTR eax, ebx
INSTR ebx, eax
cmp i, N
jl loop
pop r15
pop r14
pop r13
pop r12
pop r11
pop r10
pop r9
pop rdx
pop rcx
pop rbx
pop rax
done:
mov rsp, rbp
pop rbp
ret
.size latency, .-latency

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@@ -1,100 +0,0 @@
#define INSTR cmp
#define NINST 24
#define N edi
#define i r8d
.intel_syntax noprefix
.globl ninst
.data
ninst:
.long NINST
.text
.globl latency
.type latency, @function
.align 32
latency:
push rbp
mov rbp, rsp
xor i, i
test N, N
jle done
# create DP 1.0
vpcmpeqw xmm0, xmm0, xmm0 # all ones
vpsllq xmm0, xmm0, 54 # logical left shift: 11111110..0 (54=64-(10-1))
vpsrlq xmm0, xmm0, 2 # logical right shift: 1 bit for sign; leading mantissa bit is zero
push rax
push rbx
push rcx
push rdx
push r9
push r10
push r11
push r12
push r13
push r14
push r15
xor rax, rax
xor rbx, rbx
xor rcx, rcx
xor rdx, rdx
xor r9, r9
xor r10, r10
xor r11, r11
xor r12, r12
xor r13, r13
xor r14, r14
xor r15, r15
# copy DP 1.0
vmovq rax, xmm0
vmovq rbx, xmm0
# Create DP 2.0
add rbx, rax
# Create DP 0.5
div rax
movq rcx, rax
vmovq rax, xmm0
loop:
inc i
INSTR rdx, rax
INSTR r9, rbx
INSTR r10, rcx
INSTR rdx, rax
INSTR r9, rbx
INSTR r10, rcx
INSTR r11, rax
INSTR r12, rbx
INSTR r13, rcx
INSTR r14, rax
INSTR r15, rbx
INSTR rax, rcx
INSTR rbx, rax
INSTR rcx, rbx
INSTR rdx, rcx
INSTR r9, rax
INSTR r10, rbx
INSTR r11, rcx
INSTR r12, rax
INSTR r13, rbx
INSTR r14, rcx
INSTR r15, rax
INSTR rax, rbx
INSTR rbx, rcx
cmp i, N
jl loop
pop r15
pop r14
pop r13
pop r12
pop r11
pop r10
pop r9
pop rdx
pop rcx
pop rbx
pop rax
done:
mov rsp, rbp
pop rbp
ret
.size latency, .-latency

View File

@@ -1,100 +0,0 @@
#define INSTR cmp
#define NINST 24
#define N edi
#define i r8d
.intel_syntax noprefix
.globl ninst
.data
ninst:
.long NINST
.text
.globl latency
.type latency, @function
.align 32
latency:
push rbp
mov rbp, rsp
xor i, i
test N, N
jle done
# create DP 1.0
vpcmpeqw xmm0, xmm0, xmm0 # all ones
vpsllq xmm0, xmm0, 54 # logical left shift: 11111110..0 (54=64-(10-1))
vpsrlq xmm0, xmm0, 2 # logical right shift: 1 bit for sign; leading mantissa bit is zero
push rax
push rbx
push rcx
push rdx
push r9
push r10
push r11
push r12
push r13
push r14
push r15
xor rax, rax
xor rbx, rbx
xor rcx, rcx
xor rdx, rdx
xor r9, r9
xor r10, r10
xor r11, r11
xor r12, r12
xor r13, r13
xor r14, r14
xor r15, r15
# copy DP 1.0
vmovq rax, xmm0
vmovq rbx, xmm0
# Create DP 2.0
add rbx, rax
# Create DP 0.5
div rax
movq rcx, rax
vmovq rax, xmm0
loop:
inc i
INSTR rax, rbx
INSTR rbx, rax
INSTR rax, rbx
INSTR rbx, rax
INSTR rax, rbx
INSTR rbx, rax
INSTR rax, rbx
INSTR rbx, rax
INSTR rax, rbx
INSTR rbx, rax
INSTR rax, rbx
INSTR rbx, rax
INSTR rax, rbx
INSTR rbx, rax
INSTR rax, rbx
INSTR rbx, rax
INSTR rax, rbx
INSTR rbx, rax
INSTR rax, rbx
INSTR rbx, rax
INSTR rax, rbx
INSTR rbx, rax
INSTR rax, rbx
INSTR rbx, rax
cmp i, N
jl loop
pop r15
pop r14
pop r13
pop r12
pop r11
pop r10
pop r9
pop rdx
pop rcx
pop rbx
pop rax
done:
mov rsp, rbp
pop rbp
ret
.size latency, .-latency

View File

@@ -1,100 +0,0 @@
#define INSTR dec
#define NINST 24
#define N edi
#define i r8d
.intel_syntax noprefix
.globl ninst
.data
ninst:
.long NINST
.text
.globl latency
.type latency, @function
.align 32
latency:
push rbp
mov rbp, rsp
xor i, i
test N, N
jle done
# create DP 1.0
vpcmpeqw xmm0, xmm0, xmm0 # all ones
vpsllq xmm0, xmm0, 54 # logical left shift: 11111110..0 (54=64-(10-1))
vpsrlq xmm0, xmm0, 2 # logical right shift: 1 bit for sign; leading mantissa bit is zero
push rax
push rbx
push rcx
push rdx
push r9
push r10
push r11
push r12
push r13
push r14
push r15
xor rax, rax
xor rbx, rbx
xor rcx, rcx
xor rdx, rdx
xor r9, r9
xor r10, r10
xor r11, r11
xor r12, r12
xor r13, r13
xor r14, r14
xor r15, r15
# copy DP 1.0
vmovq rax, xmm0
vmovq rbx, xmm0
# Create DP 2.0
add rbx, rax
# Create DP 0.5
div rax
movq rcx, rax
vmovq rax, xmm0
loop:
inc i
INSTR edx
INSTR r9d
INSTR r10d
INSTR edx
INSTR r9d
INSTR r10d
INSTR r11d
INSTR r12d
INSTR r13d
INSTR r14d
INSTR r15d
INSTR eax
INSTR ebx
INSTR ecx
INSTR edx
INSTR r9d
INSTR r10d
INSTR r11d
INSTR r12d
INSTR r13d
INSTR r14d
INSTR r15d
INSTR eax
INSTR ebx
cmp i, N
jl loop
pop r15
pop r14
pop r13
pop r12
pop r11
pop r10
pop r9
pop rdx
pop rcx
pop rbx
pop rax
done:
mov rsp, rbp
pop rbp
ret
.size latency, .-latency

View File

@@ -1,100 +0,0 @@
#define INSTR dec
#define NINST 24
#define N edi
#define i r8d
.intel_syntax noprefix
.globl ninst
.data
ninst:
.long NINST
.text
.globl latency
.type latency, @function
.align 32
latency:
push rbp
mov rbp, rsp
xor i, i
test N, N
jle done
# create DP 1.0
vpcmpeqw xmm0, xmm0, xmm0 # all ones
vpsllq xmm0, xmm0, 54 # logical left shift: 11111110..0 (54=64-(10-1))
vpsrlq xmm0, xmm0, 2 # logical right shift: 1 bit for sign; leading mantissa bit is zero
push rax
push rbx
push rcx
push rdx
push r9
push r10
push r11
push r12
push r13
push r14
push r15
xor rax, rax
xor rbx, rbx
xor rcx, rcx
xor rdx, rdx
xor r9, r9
xor r10, r10
xor r11, r11
xor r12, r12
xor r13, r13
xor r14, r14
xor r15, r15
# copy DP 1.0
vmovq rax, xmm0
vmovq rbx, xmm0
# Create DP 2.0
add rbx, rax
# Create DP 0.5
div rax
movq rcx, rax
vmovq rax, xmm0
loop:
inc i
INSTR eax
INSTR eax
INSTR eax
INSTR eax
INSTR eax
INSTR eax
INSTR eax
INSTR eax
INSTR eax
INSTR eax
INSTR eax
INSTR eax
INSTR eax
INSTR eax
INSTR eax
INSTR eax
INSTR eax
INSTR eax
INSTR eax
INSTR eax
INSTR eax
INSTR eax
INSTR eax
INSTR eax
cmp i, N
jl loop
pop r15
pop r14
pop r13
pop r12
pop r11
pop r10
pop r9
pop rdx
pop rcx
pop rbx
pop rax
done:
mov rsp, rbp
pop rbp
ret
.size latency, .-latency

View File

@@ -1,100 +0,0 @@
#define INSTR inc
#define NINST 24
#define N edi
#define i r8d
.intel_syntax noprefix
.globl ninst
.data
ninst:
.long NINST
.text
.globl latency
.type latency, @function
.align 32
latency:
push rbp
mov rbp, rsp
xor i, i
test N, N
jle done
# create DP 1.0
vpcmpeqw xmm0, xmm0, xmm0 # all ones
vpsllq xmm0, xmm0, 54 # logical left shift: 11111110..0 (54=64-(10-1))
vpsrlq xmm0, xmm0, 2 # logical right shift: 1 bit for sign; leading mantissa bit is zero
push rax
push rbx
push rcx
push rdx
push r9
push r10
push r11
push r12
push r13
push r14
push r15
xor rax, rax
xor rbx, rbx
xor rcx, rcx
xor rdx, rdx
xor r9, r9
xor r10, r10
xor r11, r11
xor r12, r12
xor r13, r13
xor r14, r14
xor r15, r15
# copy DP 1.0
vmovq rax, xmm0
vmovq rbx, xmm0
# Create DP 2.0
add rbx, rax
# Create DP 0.5
div rax
movq rcx, rax
vmovq rax, xmm0
loop:
inc i
INSTR rdx
INSTR r9
INSTR r10
INSTR rdx
INSTR r9
INSTR r10
INSTR r11
INSTR r12
INSTR r13
INSTR r14
INSTR r15
INSTR rax
INSTR rbx
INSTR rcx
INSTR rdx
INSTR r9
INSTR r10
INSTR r11
INSTR r12
INSTR r13
INSTR r14
INSTR r15
INSTR rax
INSTR rbx
cmp i, N
jl loop
pop r15
pop r14
pop r13
pop r12
pop r11
pop r10
pop r9
pop rdx
pop rcx
pop rbx
pop rax
done:
mov rsp, rbp
pop rbp
ret
.size latency, .-latency

View File

@@ -1,100 +0,0 @@
#define INSTR inc
#define NINST 24
#define N edi
#define i r8d
.intel_syntax noprefix
.globl ninst
.data
ninst:
.long NINST
.text
.globl latency
.type latency, @function
.align 32
latency:
push rbp
mov rbp, rsp
xor i, i
test N, N
jle done
# create DP 1.0
vpcmpeqw xmm0, xmm0, xmm0 # all ones
vpsllq xmm0, xmm0, 54 # logical left shift: 11111110..0 (54=64-(10-1))
vpsrlq xmm0, xmm0, 2 # logical right shift: 1 bit for sign; leading mantissa bit is zero
push rax
push rbx
push rcx
push rdx
push r9
push r10
push r11
push r12
push r13
push r14
push r15
xor rax, rax
xor rbx, rbx
xor rcx, rcx
xor rdx, rdx
xor r9, r9
xor r10, r10
xor r11, r11
xor r12, r12
xor r13, r13
xor r14, r14
xor r15, r15
# copy DP 1.0
vmovq rax, xmm0
vmovq rbx, xmm0
# Create DP 2.0
add rbx, rax
# Create DP 0.5
div rax
movq rcx, rax
vmovq rax, xmm0
loop:
inc i
INSTR rax
INSTR rax
INSTR rax
INSTR rax
INSTR rax
INSTR rax
INSTR rax
INSTR rax
INSTR rax
INSTR rax
INSTR rax
INSTR rax
INSTR rax
INSTR rax
INSTR rax
INSTR rax
INSTR rax
INSTR rax
INSTR rax
INSTR rax
INSTR rax
INSTR rax
INSTR rax
INSTR rax
cmp i, N
jl loop
pop r15
pop r14
pop r13
pop r12
pop r11
pop r10
pop r9
pop rdx
pop rcx
pop rbx
pop rax
done:
mov rsp, rbp
pop rbp
ret
.size latency, .-latency

View File

@@ -1,82 +0,0 @@
#define INSTR janadd
#define NINST 6
#define N edi
#define i r8d
.intel_syntax noprefix
.globl ninst
.data
ninst:
.long NINST
.text
.globl latency
.type latency, @function
.align 32
latency:
push rbp
mov rbp, rsp
xor i, i
test N, N
jle done
# create DP 1.0
vpcmpeqw xmm0, xmm0, xmm0 # all ones
vpsllq xmm0, xmm0, 54 # logical left shift: 11111110..0 (54=64-(10-1))
vpsrlq xmm0, xmm0, 2 # logical right shift: 1 bit for sign; leading mantissa bit is zero
push rax
push rbx
push rcx
push rdx
push r9
push r10
push r11
push r12
push r13
push r14
push r15
xor rax, rax
xor rbx, rbx
xor rcx, rcx
xor rdx, rdx
xor r9, r9
xor r10, r10
xor r11, r11
xor r12, r12
xor r13, r13
xor r14, r14
xor r15, r15
# copy DP 1.0
vmovq rax, xmm0
vmovq rbx, xmm0
# Create DP 2.0
add rbx, rax
# Create DP 0.5
div rax
movq rcx, rax
vmovq rax, xmm0
loop:
inc i
INSTR rdx, eax
INSTR r9, ebx
INSTR r10, ecx
INSTR rdx, eax
INSTR r9, ebx
INSTR r10, ecx
cmp i, N
jl loop
pop r15
pop r14
pop r13
pop r12
pop r11
pop r10
pop r9
pop rdx
pop rcx
pop rbx
pop rax
done:
mov rsp, rbp
pop rbp
ret
.size latency, .-latency

View File

@@ -1,82 +0,0 @@
#define INSTR janadd
#define NINST 6
#define N edi
#define i r8d
.intel_syntax noprefix
.globl ninst
.data
ninst:
.long NINST
.text
.globl latency
.type latency, @function
.align 32
latency:
push rbp
mov rbp, rsp
xor i, i
test N, N
jle done
# create DP 1.0
vpcmpeqw xmm0, xmm0, xmm0 # all ones
vpsllq xmm0, xmm0, 54 # logical left shift: 11111110..0 (54=64-(10-1))
vpsrlq xmm0, xmm0, 2 # logical right shift: 1 bit for sign; leading mantissa bit is zero
push rax
push rbx
push rcx
push rdx
push r9
push r10
push r11
push r12
push r13
push r14
push r15
xor rax, rax
xor rbx, rbx
xor rcx, rcx
xor rdx, rdx
xor r9, r9
xor r10, r10
xor r11, r11
xor r12, r12
xor r13, r13
xor r14, r14
xor r15, r15
# copy DP 1.0
vmovq rax, xmm0
vmovq rbx, xmm0
# Create DP 2.0
add rbx, rax
# Create DP 0.5
div rax
movq rcx, rax
vmovq rax, xmm0
loop:
inc i
INSTR rax, eax
INSTR rax, eax
INSTR rax, eax
INSTR rax, eax
INSTR rax, eax
INSTR rax, eax
cmp i, N
jl loop
pop r15
pop r14
pop r13
pop r12
pop r11
pop r10
pop r9
pop rdx
pop rcx
pop rbx
pop rax
done:
mov rsp, rbp
pop rbp
ret
.size latency, .-latency

View File

@@ -1,82 +0,0 @@
#define INSTR janadd
#define NINST 6
#define N edi
#define i r8d
.intel_syntax noprefix
.globl ninst
.data
ninst:
.long NINST
.text
.globl latency
.type latency, @function
.align 32
latency:
push rbp
mov rbp, rsp
xor i, i
test N, N
jle done
# create DP 1.0
vpcmpeqw xmm0, xmm0, xmm0 # all ones
vpsllq xmm0, xmm0, 54 # logical left shift: 11111110..0 (54=64-(10-1))
vpsrlq xmm0, xmm0, 2 # logical right shift: 1 bit for sign; leading mantissa bit is zero
push rax
push rbx
push rcx
push rdx
push r9
push r10
push r11
push r12
push r13
push r14
push r15
xor rax, rax
xor rbx, rbx
xor rcx, rcx
xor rdx, rdx
xor r9, r9
xor r10, r10
xor r11, r11
xor r12, r12
xor r13, r13
xor r14, r14
xor r15, r15
# copy DP 1.0
vmovq rax, xmm0
vmovq rbx, xmm0
# Create DP 2.0
add rbx, rax
# Create DP 0.5
div rax
movq rcx, rax
vmovq rax, xmm0
loop:
inc i
INSTR rdx, eax
INSTR r9, ebx
INSTR r10, ecx
INSTR rdx, eax
INSTR r9, ebx
INSTR r10, ecx
cmp i, N
jl loop
pop r15
pop r14
pop r13
pop r12
pop r11
pop r10
pop r9
pop rdx
pop rcx
pop rbx
pop rax
done:
mov rsp, rbp
pop rbp
ret
.size latency, .-latency

View File

@@ -1,82 +0,0 @@
#define INSTR janadd
#define NINST 6
#define N edi
#define i r8d
.intel_syntax noprefix
.globl ninst
.data
ninst:
.long NINST
.text
.globl latency
.type latency, @function
.align 32
latency:
push rbp
mov rbp, rsp
xor i, i
test N, N
jle done
# create DP 1.0
vpcmpeqw xmm0, xmm0, xmm0 # all ones
vpsllq xmm0, xmm0, 54 # logical left shift: 11111110..0 (54=64-(10-1))
vpsrlq xmm0, xmm0, 2 # logical right shift: 1 bit for sign; leading mantissa bit is zero
push rax
push rbx
push rcx
push rdx
push r9
push r10
push r11
push r12
push r13
push r14
push r15
xor rax, rax
xor rbx, rbx
xor rcx, rcx
xor rdx, rdx
xor r9, r9
xor r10, r10
xor r11, r11
xor r12, r12
xor r13, r13
xor r14, r14
xor r15, r15
# copy DP 1.0
vmovq rax, xmm0
vmovq rbx, xmm0
# Create DP 2.0
add rbx, rax
# Create DP 0.5
div rax
movq rcx, rax
vmovq rax, xmm0
loop:
inc i
INSTR rax, eax
INSTR rax, eax
INSTR rax, eax
INSTR rax, eax
INSTR rax, eax
INSTR rax, eax
cmp i, N
jl loop
pop r15
pop r14
pop r13
pop r12
pop r11
pop r10
pop r9
pop rdx
pop rcx
pop rbx
pop rax
done:
mov rsp, rbp
pop rbp
ret
.size latency, .-latency

View File

@@ -1,100 +0,0 @@
#define INSTR mov
#define NINST 24
#define N edi
#define i r8d
.intel_syntax noprefix
.globl ninst
.data
ninst:
.long NINST
.text
.globl latency
.type latency, @function
.align 32
latency:
push rbp
mov rbp, rsp
xor i, i
test N, N
jle done
# create DP 1.0
vpcmpeqw xmm0, xmm0, xmm0 # all ones
vpsllq xmm0, xmm0, 54 # logical left shift: 11111110..0 (54=64-(10-1))
vpsrlq xmm0, xmm0, 2 # logical right shift: 1 bit for sign; leading mantissa bit is zero
push rax
push rbx
push rcx
push rdx
push r9
push r10
push r11
push r12
push r13
push r14
push r15
xor rax, rax
xor rbx, rbx
xor rcx, rcx
xor rdx, rdx
xor r9, r9
xor r10, r10
xor r11, r11
xor r12, r12
xor r13, r13
xor r14, r14
xor r15, r15
# copy DP 1.0
vmovq rax, xmm0
vmovq rbx, xmm0
# Create DP 2.0
add rbx, rax
# Create DP 0.5
div rax
movq rcx, rax
vmovq rax, xmm0
loop:
inc i
INSTR rdx, rax
INSTR r9, rbx
INSTR r10, rcx
INSTR rdx, rax
INSTR r9, rbx
INSTR r10, rcx
INSTR r11, rax
INSTR r12, rbx
INSTR r13, rcx
INSTR r14, rax
INSTR r15, rbx
INSTR rax, rcx
INSTR rbx, rax
INSTR rcx, rbx
INSTR rdx, rcx
INSTR r9, rax
INSTR r10, rbx
INSTR r11, rcx
INSTR r12, rax
INSTR r13, rbx
INSTR r14, rcx
INSTR r15, rax
INSTR rax, rbx
INSTR rbx, rcx
cmp i, N
jl loop
pop r15
pop r14
pop r13
pop r12
pop r11
pop r10
pop r9
pop rdx
pop rcx
pop rbx
pop rax
done:
mov rsp, rbp
pop rbp
ret
.size latency, .-latency

View File

@@ -1,100 +0,0 @@
#define INSTR mov
#define NINST 24
#define N edi
#define i r8d
.intel_syntax noprefix
.globl ninst
.data
ninst:
.long NINST
.text
.globl latency
.type latency, @function
.align 32
latency:
push rbp
mov rbp, rsp
xor i, i
test N, N
jle done
# create DP 1.0
vpcmpeqw xmm0, xmm0, xmm0 # all ones
vpsllq xmm0, xmm0, 54 # logical left shift: 11111110..0 (54=64-(10-1))
vpsrlq xmm0, xmm0, 2 # logical right shift: 1 bit for sign; leading mantissa bit is zero
push rax
push rbx
push rcx
push rdx
push r9
push r10
push r11
push r12
push r13
push r14
push r15
xor rax, rax
xor rbx, rbx
xor rcx, rcx
xor rdx, rdx
xor r9, r9
xor r10, r10
xor r11, r11
xor r12, r12
xor r13, r13
xor r14, r14
xor r15, r15
# copy DP 1.0
vmovq rax, xmm0
vmovq rbx, xmm0
# Create DP 2.0
add rbx, rax
# Create DP 0.5
div rax
movq rcx, rax
vmovq rax, xmm0
loop:
inc i
INSTR rax, rbx
INSTR rbx, rax
INSTR rax, rbx
INSTR rbx, rax
INSTR rax, rbx
INSTR rbx, rax
INSTR rax, rbx
INSTR rbx, rax
INSTR rax, rbx
INSTR rbx, rax
INSTR rax, rbx
INSTR rbx, rax
INSTR rax, rbx
INSTR rbx, rax
INSTR rax, rbx
INSTR rbx, rax
INSTR rax, rbx
INSTR rbx, rax
INSTR rax, rbx
INSTR rbx, rax
INSTR rax, rbx
INSTR rbx, rax
INSTR rax, rbx
INSTR rbx, rax
cmp i, N
jl loop
pop r15
pop r14
pop r13
pop r12
pop r11
pop r10
pop r9
pop rdx
pop rcx
pop rbx
pop rax
done:
mov rsp, rbp
pop rbp
ret
.size latency, .-latency

View File

@@ -1,100 +0,0 @@
#define INSTR movslq
#define NINST 24
#define N edi
#define i r8d
.intel_syntax noprefix
.globl ninst
.data
ninst:
.long NINST
.text
.globl latency
.type latency, @function
.align 32
latency:
push rbp
mov rbp, rsp
xor i, i
test N, N
jle done
# create DP 1.0
vpcmpeqw xmm0, xmm0, xmm0 # all ones
vpsllq xmm0, xmm0, 54 # logical left shift: 11111110..0 (54=64-(10-1))
vpsrlq xmm0, xmm0, 2 # logical right shift: 1 bit for sign; leading mantissa bit is zero
push rax
push rbx
push rcx
push rdx
push r9
push r10
push r11
push r12
push r13
push r14
push r15
xor rax, rax
xor rbx, rbx
xor rcx, rcx
xor rdx, rdx
xor r9, r9
xor r10, r10
xor r11, r11
xor r12, r12
xor r13, r13
xor r14, r14
xor r15, r15
# copy DP 1.0
vmovq rax, xmm0
vmovq rbx, xmm0
# Create DP 2.0
add rbx, rax
# Create DP 0.5
div rax
movq rcx, rax
vmovq rax, xmm0
loop:
inc i
INSTR rdx, eax
INSTR r9, ebx
INSTR r10, ecx
INSTR rdx, eax
INSTR r9, ebx
INSTR r10, ecx
INSTR r11, eax
INSTR r12, ebx
INSTR r13, ecx
INSTR r14, eax
INSTR r15, ebx
INSTR rax, ecx
INSTR rbx, eax
INSTR rcx, ebx
INSTR rdx, ecx
INSTR r9, eax
INSTR r10, ebx
INSTR r11, ecx
INSTR r12, eax
INSTR r13, ebx
INSTR r14, ecx
INSTR r15, eax
INSTR rax, ebx
INSTR rbx, ecx
cmp i, N
jl loop
pop r15
pop r14
pop r13
pop r12
pop r11
pop r10
pop r9
pop rdx
pop rcx
pop rbx
pop rax
done:
mov rsp, rbp
pop rbp
ret
.size latency, .-latency

View File

@@ -1,100 +0,0 @@
#define INSTR movslq
#define NINST 24
#define N edi
#define i r8d
.intel_syntax noprefix
.globl ninst
.data
ninst:
.long NINST
.text
.globl latency
.type latency, @function
.align 32
latency:
push rbp
mov rbp, rsp
xor i, i
test N, N
jle done
# create DP 1.0
vpcmpeqw xmm0, xmm0, xmm0 # all ones
vpsllq xmm0, xmm0, 54 # logical left shift: 11111110..0 (54=64-(10-1))
vpsrlq xmm0, xmm0, 2 # logical right shift: 1 bit for sign; leading mantissa bit is zero
push rax
push rbx
push rcx
push rdx
push r9
push r10
push r11
push r12
push r13
push r14
push r15
xor rax, rax
xor rbx, rbx
xor rcx, rcx
xor rdx, rdx
xor r9, r9
xor r10, r10
xor r11, r11
xor r12, r12
xor r13, r13
xor r14, r14
xor r15, r15
# copy DP 1.0
vmovq rax, xmm0
vmovq rbx, xmm0
# Create DP 2.0
add rbx, rax
# Create DP 0.5
div rax
movq rcx, rax
vmovq rax, xmm0
loop:
inc i
INSTR rax, eax
INSTR rax, eax
INSTR rax, eax
INSTR rax, eax
INSTR rax, eax
INSTR rax, eax
INSTR rax, eax
INSTR rax, eax
INSTR rax, eax
INSTR rax, eax
INSTR rax, eax
INSTR rax, eax
INSTR rax, eax
INSTR rax, eax
INSTR rax, eax
INSTR rax, eax
INSTR rax, eax
INSTR rax, eax
INSTR rax, eax
INSTR rax, eax
INSTR rax, eax
INSTR rax, eax
INSTR rax, eax
INSTR rax, eax
cmp i, N
jl loop
pop r15
pop r14
pop r13
pop r12
pop r11
pop r10
pop r9
pop rdx
pop rcx
pop rbx
pop rax
done:
mov rsp, rbp
pop rbp
ret
.size latency, .-latency

View File

@@ -1,100 +0,0 @@
#define INSTR movzbl
#define NINST 24
#define N edi
#define i r8d
.intel_syntax noprefix
.globl ninst
.data
ninst:
.long NINST
.text
.globl latency
.type latency, @function
.align 32
latency:
push rbp
mov rbp, rsp
xor i, i
test N, N
jle done
# create DP 1.0
vpcmpeqw xmm0, xmm0, xmm0 # all ones
vpsllq xmm0, xmm0, 54 # logical left shift: 11111110..0 (54=64-(10-1))
vpsrlq xmm0, xmm0, 2 # logical right shift: 1 bit for sign; leading mantissa bit is zero
push rax
push rbx
push rcx
push rdx
push r9
push r10
push r11
push r12
push r13
push r14
push r15
xor rax, rax
xor rbx, rbx
xor rcx, rcx
xor rdx, rdx
xor r9, r9
xor r10, r10
xor r11, r11
xor r12, r12
xor r13, r13
xor r14, r14
xor r15, r15
# copy DP 1.0
vmovq rax, xmm0
vmovq rbx, xmm0
# Create DP 2.0
add rbx, rax
# Create DP 0.5
div rax
movq rcx, rax
vmovq rax, xmm0
loop:
inc i
INSTR edx, al
INSTR r9d, bl
INSTR r10d, cl
INSTR edx, al
INSTR r9d, bl
INSTR r10d, cl
INSTR r11d, al
INSTR r12d, bl
INSTR r13d, cl
INSTR r14d, al
INSTR r15d, bl
INSTR eax, cl
INSTR ebx, al
INSTR ecx, bl
INSTR edx, cl
INSTR r9d, al
INSTR r10d, bl
INSTR r11d, cl
INSTR r12d, al
INSTR r13d, bl
INSTR r14d, cl
INSTR r15d, al
INSTR eax, bl
INSTR ebx, cl
cmp i, N
jl loop
pop r15
pop r14
pop r13
pop r12
pop r11
pop r10
pop r9
pop rdx
pop rcx
pop rbx
pop rax
done:
mov rsp, rbp
pop rbp
ret
.size latency, .-latency

View File

@@ -1,100 +0,0 @@
#define INSTR movzbl
#define NINST 24
#define N edi
#define i r8d
.intel_syntax noprefix
.globl ninst
.data
ninst:
.long NINST
.text
.globl latency
.type latency, @function
.align 32
latency:
push rbp
mov rbp, rsp
xor i, i
test N, N
jle done
# create DP 1.0
vpcmpeqw xmm0, xmm0, xmm0 # all ones
vpsllq xmm0, xmm0, 54 # logical left shift: 11111110..0 (54=64-(10-1))
vpsrlq xmm0, xmm0, 2 # logical right shift: 1 bit for sign; leading mantissa bit is zero
push rax
push rbx
push rcx
push rdx
push r9
push r10
push r11
push r12
push r13
push r14
push r15
xor rax, rax
xor rbx, rbx
xor rcx, rcx
xor rdx, rdx
xor r9, r9
xor r10, r10
xor r11, r11
xor r12, r12
xor r13, r13
xor r14, r14
xor r15, r15
# copy DP 1.0
vmovq rax, xmm0
vmovq rbx, xmm0
# Create DP 2.0
add rbx, rax
# Create DP 0.5
div rax
movq rcx, rax
vmovq rax, xmm0
loop:
inc i
INSTR eax, al
INSTR eax, al
INSTR eax, al
INSTR eax, al
INSTR eax, al
INSTR eax, al
INSTR eax, al
INSTR eax, al
INSTR eax, al
INSTR eax, al
INSTR eax, al
INSTR eax, al
INSTR eax, al
INSTR eax, al
INSTR eax, al
INSTR eax, al
INSTR eax, al
INSTR eax, al
INSTR eax, al
INSTR eax, al
INSTR eax, al
INSTR eax, al
INSTR eax, al
INSTR eax, al
cmp i, N
jl loop
pop r15
pop r14
pop r13
pop r12
pop r11
pop r10
pop r9
pop rdx
pop rcx
pop rbx
pop rax
done:
mov rsp, rbp
pop rbp
ret
.size latency, .-latency

View File

@@ -1,100 +0,0 @@
#define INSTR neg
#define NINST 24
#define N edi
#define i r8d
.intel_syntax noprefix
.globl ninst
.data
ninst:
.long NINST
.text
.globl latency
.type latency, @function
.align 32
latency:
push rbp
mov rbp, rsp
xor i, i
test N, N
jle done
# create DP 1.0
vpcmpeqw xmm0, xmm0, xmm0 # all ones
vpsllq xmm0, xmm0, 54 # logical left shift: 11111110..0 (54=64-(10-1))
vpsrlq xmm0, xmm0, 2 # logical right shift: 1 bit for sign; leading mantissa bit is zero
push rax
push rbx
push rcx
push rdx
push r9
push r10
push r11
push r12
push r13
push r14
push r15
xor rax, rax
xor rbx, rbx
xor rcx, rcx
xor rdx, rdx
xor r9, r9
xor r10, r10
xor r11, r11
xor r12, r12
xor r13, r13
xor r14, r14
xor r15, r15
# copy DP 1.0
vmovq rax, xmm0
vmovq rbx, xmm0
# Create DP 2.0
add rbx, rax
# Create DP 0.5
div rax
movq rcx, rax
vmovq rax, xmm0
loop:
inc i
INSTR edx
INSTR r9d
INSTR r10d
INSTR edx
INSTR r9d
INSTR r10d
INSTR r11d
INSTR r12d
INSTR r13d
INSTR r14d
INSTR r15d
INSTR eax
INSTR ebx
INSTR ecx
INSTR edx
INSTR r9d
INSTR r10d
INSTR r11d
INSTR r12d
INSTR r13d
INSTR r14d
INSTR r15d
INSTR eax
INSTR ebx
cmp i, N
jl loop
pop r15
pop r14
pop r13
pop r12
pop r11
pop r10
pop r9
pop rdx
pop rcx
pop rbx
pop rax
done:
mov rsp, rbp
pop rbp
ret
.size latency, .-latency

View File

@@ -1,100 +0,0 @@
#define INSTR neg
#define NINST 24
#define N edi
#define i r8d
.intel_syntax noprefix
.globl ninst
.data
ninst:
.long NINST
.text
.globl latency
.type latency, @function
.align 32
latency:
push rbp
mov rbp, rsp
xor i, i
test N, N
jle done
# create DP 1.0
vpcmpeqw xmm0, xmm0, xmm0 # all ones
vpsllq xmm0, xmm0, 54 # logical left shift: 11111110..0 (54=64-(10-1))
vpsrlq xmm0, xmm0, 2 # logical right shift: 1 bit for sign; leading mantissa bit is zero
push rax
push rbx
push rcx
push rdx
push r9
push r10
push r11
push r12
push r13
push r14
push r15
xor rax, rax
xor rbx, rbx
xor rcx, rcx
xor rdx, rdx
xor r9, r9
xor r10, r10
xor r11, r11
xor r12, r12
xor r13, r13
xor r14, r14
xor r15, r15
# copy DP 1.0
vmovq rax, xmm0
vmovq rbx, xmm0
# Create DP 2.0
add rbx, rax
# Create DP 0.5
div rax
movq rcx, rax
vmovq rax, xmm0
loop:
inc i
INSTR eax
INSTR eax
INSTR eax
INSTR eax
INSTR eax
INSTR eax
INSTR eax
INSTR eax
INSTR eax
INSTR eax
INSTR eax
INSTR eax
INSTR eax
INSTR eax
INSTR eax
INSTR eax
INSTR eax
INSTR eax
INSTR eax
INSTR eax
INSTR eax
INSTR eax
INSTR eax
INSTR eax
cmp i, N
jl loop
pop r15
pop r14
pop r13
pop r12
pop r11
pop r10
pop r9
pop rdx
pop rcx
pop rbx
pop rax
done:
mov rsp, rbp
pop rbp
ret
.size latency, .-latency

View File

@@ -1,100 +0,0 @@
#define INSTR pop
#define NINST 24
#define N edi
#define i r8d
.intel_syntax noprefix
.globl ninst
.data
ninst:
.long NINST
.text
.globl latency
.type latency, @function
.align 32
latency:
push rbp
mov rbp, rsp
xor i, i
test N, N
jle done
# create DP 1.0
vpcmpeqw xmm0, xmm0, xmm0 # all ones
vpsllq xmm0, xmm0, 54 # logical left shift: 11111110..0 (54=64-(10-1))
vpsrlq xmm0, xmm0, 2 # logical right shift: 1 bit for sign; leading mantissa bit is zero
push rax
push rbx
push rcx
push rdx
push r9
push r10
push r11
push r12
push r13
push r14
push r15
xor rax, rax
xor rbx, rbx
xor rcx, rcx
xor rdx, rdx
xor r9, r9
xor r10, r10
xor r11, r11
xor r12, r12
xor r13, r13
xor r14, r14
xor r15, r15
# copy DP 1.0
vmovq rax, xmm0
vmovq rbx, xmm0
# Create DP 2.0
add rbx, rax
# Create DP 0.5
div rax
movq rcx, rax
vmovq rax, xmm0
loop:
inc i
INSTR rdx
INSTR r9
INSTR r10
INSTR rdx
INSTR r9
INSTR r10
INSTR r11
INSTR r12
INSTR r13
INSTR r14
INSTR r15
INSTR rax
INSTR rbx
INSTR rcx
INSTR rdx
INSTR r9
INSTR r10
INSTR r11
INSTR r12
INSTR r13
INSTR r14
INSTR r15
INSTR rax
INSTR rbx
cmp i, N
jl loop
pop r15
pop r14
pop r13
pop r12
pop r11
pop r10
pop r9
pop rdx
pop rcx
pop rbx
pop rax
done:
mov rsp, rbp
pop rbp
ret
.size latency, .-latency

View File

@@ -1,100 +0,0 @@
#define INSTR pop
#define NINST 24
#define N edi
#define i r8d
.intel_syntax noprefix
.globl ninst
.data
ninst:
.long NINST
.text
.globl latency
.type latency, @function
.align 32
latency:
push rbp
mov rbp, rsp
xor i, i
test N, N
jle done
# create DP 1.0
vpcmpeqw xmm0, xmm0, xmm0 # all ones
vpsllq xmm0, xmm0, 54 # logical left shift: 11111110..0 (54=64-(10-1))
vpsrlq xmm0, xmm0, 2 # logical right shift: 1 bit for sign; leading mantissa bit is zero
push rax
push rbx
push rcx
push rdx
push r9
push r10
push r11
push r12
push r13
push r14
push r15
xor rax, rax
xor rbx, rbx
xor rcx, rcx
xor rdx, rdx
xor r9, r9
xor r10, r10
xor r11, r11
xor r12, r12
xor r13, r13
xor r14, r14
xor r15, r15
# copy DP 1.0
vmovq rax, xmm0
vmovq rbx, xmm0
# Create DP 2.0
add rbx, rax
# Create DP 0.5
div rax
movq rcx, rax
vmovq rax, xmm0
loop:
inc i
INSTR rax
INSTR rax
INSTR rax
INSTR rax
INSTR rax
INSTR rax
INSTR rax
INSTR rax
INSTR rax
INSTR rax
INSTR rax
INSTR rax
INSTR rax
INSTR rax
INSTR rax
INSTR rax
INSTR rax
INSTR rax
INSTR rax
INSTR rax
INSTR rax
INSTR rax
INSTR rax
INSTR rax
cmp i, N
jl loop
pop r15
pop r14
pop r13
pop r12
pop r11
pop r10
pop r9
pop rdx
pop rcx
pop rbx
pop rax
done:
mov rsp, rbp
pop rbp
ret
.size latency, .-latency

View File

@@ -1,100 +0,0 @@
#define INSTR sub
#define NINST 24
#define N edi
#define i r8d
.intel_syntax noprefix
.globl ninst
.data
ninst:
.long NINST
.text
.globl latency
.type latency, @function
.align 32
latency:
push rbp
mov rbp, rsp
xor i, i
test N, N
jle done
# create DP 1.0
vpcmpeqw xmm0, xmm0, xmm0 # all ones
vpsllq xmm0, xmm0, 54 # logical left shift: 11111110..0 (54=64-(10-1))
vpsrlq xmm0, xmm0, 2 # logical right shift: 1 bit for sign; leading mantissa bit is zero
push rax
push rbx
push rcx
push rdx
push r9
push r10
push r11
push r12
push r13
push r14
push r15
xor rax, rax
xor rbx, rbx
xor rcx, rcx
xor rdx, rdx
xor r9, r9
xor r10, r10
xor r11, r11
xor r12, r12
xor r13, r13
xor r14, r14
xor r15, r15
# copy DP 1.0
vmovq rax, xmm0
vmovq rbx, xmm0
# Create DP 2.0
add rbx, rax
# Create DP 0.5
div rax
movq rcx, rax
vmovq rax, xmm0
loop:
inc i
INSTR rdx, rax
INSTR r9, rbx
INSTR r10, rcx
INSTR rdx, rax
INSTR r9, rbx
INSTR r10, rcx
INSTR r11, rax
INSTR r12, rbx
INSTR r13, rcx
INSTR r14, rax
INSTR r15, rbx
INSTR rax, rcx
INSTR rbx, rax
INSTR rcx, rbx
INSTR rdx, rcx
INSTR r9, rax
INSTR r10, rbx
INSTR r11, rcx
INSTR r12, rax
INSTR r13, rbx
INSTR r14, rcx
INSTR r15, rax
INSTR rax, rbx
INSTR rbx, rcx
cmp i, N
jl loop
pop r15
pop r14
pop r13
pop r12
pop r11
pop r10
pop r9
pop rdx
pop rcx
pop rbx
pop rax
done:
mov rsp, rbp
pop rbp
ret
.size latency, .-latency

View File

@@ -1,100 +0,0 @@
#define INSTR sub
#define NINST 24
#define N edi
#define i r8d
.intel_syntax noprefix
.globl ninst
.data
ninst:
.long NINST
.text
.globl latency
.type latency, @function
.align 32
latency:
push rbp
mov rbp, rsp
xor i, i
test N, N
jle done
# create DP 1.0
vpcmpeqw xmm0, xmm0, xmm0 # all ones
vpsllq xmm0, xmm0, 54 # logical left shift: 11111110..0 (54=64-(10-1))
vpsrlq xmm0, xmm0, 2 # logical right shift: 1 bit for sign; leading mantissa bit is zero
push rax
push rbx
push rcx
push rdx
push r9
push r10
push r11
push r12
push r13
push r14
push r15
xor rax, rax
xor rbx, rbx
xor rcx, rcx
xor rdx, rdx
xor r9, r9
xor r10, r10
xor r11, r11
xor r12, r12
xor r13, r13
xor r14, r14
xor r15, r15
# copy DP 1.0
vmovq rax, xmm0
vmovq rbx, xmm0
# Create DP 2.0
add rbx, rax
# Create DP 0.5
div rax
movq rcx, rax
vmovq rax, xmm0
loop:
inc i
INSTR rax, rbx
INSTR rbx, rax
INSTR rax, rbx
INSTR rbx, rax
INSTR rax, rbx
INSTR rbx, rax
INSTR rax, rbx
INSTR rbx, rax
INSTR rax, rbx
INSTR rbx, rax
INSTR rax, rbx
INSTR rbx, rax
INSTR rax, rbx
INSTR rbx, rax
INSTR rax, rbx
INSTR rbx, rax
INSTR rax, rbx
INSTR rbx, rax
INSTR rax, rbx
INSTR rbx, rax
INSTR rax, rbx
INSTR rbx, rax
INSTR rax, rbx
INSTR rbx, rax
cmp i, N
jl loop
pop r15
pop r14
pop r13
pop r12
pop r11
pop r10
pop r9
pop rdx
pop rcx
pop rbx
pop rax
done:
mov rsp, rbp
pop rbp
ret
.size latency, .-latency

View File

@@ -1,100 +0,0 @@
#define INSTR test
#define NINST 24
#define N edi
#define i r8d
.intel_syntax noprefix
.globl ninst
.data
ninst:
.long NINST
.text
.globl latency
.type latency, @function
.align 32
latency:
push rbp
mov rbp, rsp
xor i, i
test N, N
jle done
# create DP 1.0
vpcmpeqw xmm0, xmm0, xmm0 # all ones
vpsllq xmm0, xmm0, 54 # logical left shift: 11111110..0 (54=64-(10-1))
vpsrlq xmm0, xmm0, 2 # logical right shift: 1 bit for sign; leading mantissa bit is zero
push rax
push rbx
push rcx
push rdx
push r9
push r10
push r11
push r12
push r13
push r14
push r15
xor rax, rax
xor rbx, rbx
xor rcx, rcx
xor rdx, rdx
xor r9, r9
xor r10, r10
xor r11, r11
xor r12, r12
xor r13, r13
xor r14, r14
xor r15, r15
# copy DP 1.0
vmovq rax, xmm0
vmovq rbx, xmm0
# Create DP 2.0
add rbx, rax
# Create DP 0.5
div rax
movq rcx, rax
vmovq rax, xmm0
loop:
inc i
INSTR rdx, rax
INSTR r9, rbx
INSTR r10, rcx
INSTR rdx, rax
INSTR r9, rbx
INSTR r10, rcx
INSTR r11, rax
INSTR r12, rbx
INSTR r13, rcx
INSTR r14, rax
INSTR r15, rbx
INSTR rax, rcx
INSTR rbx, rax
INSTR rcx, rbx
INSTR rdx, rcx
INSTR r9, rax
INSTR r10, rbx
INSTR r11, rcx
INSTR r12, rax
INSTR r13, rbx
INSTR r14, rcx
INSTR r15, rax
INSTR rax, rbx
INSTR rbx, rcx
cmp i, N
jl loop
pop r15
pop r14
pop r13
pop r12
pop r11
pop r10
pop r9
pop rdx
pop rcx
pop rbx
pop rax
done:
mov rsp, rbp
pop rbp
ret
.size latency, .-latency

View File

@@ -1,100 +0,0 @@
#define INSTR test
#define NINST 24
#define N edi
#define i r8d
.intel_syntax noprefix
.globl ninst
.data
ninst:
.long NINST
.text
.globl latency
.type latency, @function
.align 32
latency:
push rbp
mov rbp, rsp
xor i, i
test N, N
jle done
# create DP 1.0
vpcmpeqw xmm0, xmm0, xmm0 # all ones
vpsllq xmm0, xmm0, 54 # logical left shift: 11111110..0 (54=64-(10-1))
vpsrlq xmm0, xmm0, 2 # logical right shift: 1 bit for sign; leading mantissa bit is zero
push rax
push rbx
push rcx
push rdx
push r9
push r10
push r11
push r12
push r13
push r14
push r15
xor rax, rax
xor rbx, rbx
xor rcx, rcx
xor rdx, rdx
xor r9, r9
xor r10, r10
xor r11, r11
xor r12, r12
xor r13, r13
xor r14, r14
xor r15, r15
# copy DP 1.0
vmovq rax, xmm0
vmovq rbx, xmm0
# Create DP 2.0
add rbx, rax
# Create DP 0.5
div rax
movq rcx, rax
vmovq rax, xmm0
loop:
inc i
INSTR rax, rbx
INSTR rbx, rax
INSTR rax, rbx
INSTR rbx, rax
INSTR rax, rbx
INSTR rbx, rax
INSTR rax, rbx
INSTR rbx, rax
INSTR rax, rbx
INSTR rbx, rax
INSTR rax, rbx
INSTR rbx, rax
INSTR rax, rbx
INSTR rbx, rax
INSTR rax, rbx
INSTR rbx, rax
INSTR rax, rbx
INSTR rbx, rax
INSTR rax, rbx
INSTR rbx, rax
INSTR rax, rbx
INSTR rbx, rax
INSTR rax, rbx
INSTR rbx, rax
cmp i, N
jl loop
pop r15
pop r14
pop r13
pop r12
pop r11
pop r10
pop r9
pop rdx
pop rcx
pop rbx
pop rax
done:
mov rsp, rbp
pop rbp
ret
.size latency, .-latency

View File

@@ -1,67 +0,0 @@
#define INSTR vaddpd
#define NINST 24
#define N edi
#define i r8d
.intel_syntax noprefix
.globl ninst
.data
ninst:
.long NINST
.text
.globl latency
.type latency, @function
.align 32
latency:
push rbp
mov rbp, rsp
xor i, i
test N, N
jle done
# create DP 1.0
vpcmpeqw xmm0, xmm0, xmm0 # all ones
vpsllq xmm0, xmm0, 54 # logical left shift: 11111110..0 (54=64-(10-1))
vpsrlq xmm0, xmm0, 2 # logical right shift: 1 bit for sign; leading mantissa bit is zero
# expand from SSE to AVX
vinsertf128 ymm0, ymm0, xmm0, 0x1
# copy DP 1.0
vmovaps ymm0, ymm0
vmovaps ymm1, ymm0
# Create DP 2.0
vaddpd ymm1, ymm1, ymm1
# Create DP 0.5
vdivpd ymm2, ymm0, ymm1
loop:
inc i
INSTR ymm3, ymm0, ymm0
INSTR ymm4, ymm1, ymm1
INSTR ymm5, ymm2, ymm2
INSTR ymm3, ymm0, ymm0
INSTR ymm4, ymm1, ymm1
INSTR ymm5, ymm2, ymm2
INSTR ymm6, ymm0, ymm0
INSTR ymm7, ymm1, ymm1
INSTR ymm8, ymm2, ymm2
INSTR ymm9, ymm0, ymm0
INSTR ymm10, ymm1, ymm1
INSTR ymm11, ymm2, ymm2
INSTR ymm12, ymm0, ymm0
INSTR ymm13, ymm1, ymm1
INSTR ymm14, ymm2, ymm2
INSTR ymm15, ymm0, ymm0
INSTR ymm16, ymm1, ymm1
INSTR ymm17, ymm2, ymm2
INSTR ymm18, ymm0, ymm0
INSTR ymm19, ymm1, ymm1
INSTR ymm20, ymm2, ymm2
INSTR ymm21, ymm0, ymm0
INSTR ymm22, ymm1, ymm1
INSTR ymm23, ymm2, ymm2
cmp i, N
jl loop
done:
mov rsp, rbp
pop rbp
ret
.size latency, .-latency

View File

@@ -1,67 +0,0 @@
#define INSTR vaddpd
#define NINST 24
#define N edi
#define i r8d
.intel_syntax noprefix
.globl ninst
.data
ninst:
.long NINST
.text
.globl latency
.type latency, @function
.align 32
latency:
push rbp
mov rbp, rsp
xor i, i
test N, N
jle done
# create DP 1.0
vpcmpeqw xmm0, xmm0, xmm0 # all ones
vpsllq xmm0, xmm0, 54 # logical left shift: 11111110..0 (54=64-(10-1))
vpsrlq xmm0, xmm0, 2 # logical right shift: 1 bit for sign; leading mantissa bit is zero
# expand from SSE to AVX
vinsertf128 ymm0, ymm0, xmm0, 0x1
# copy DP 1.0
vmovaps ymm0, ymm0
vmovaps ymm1, ymm0
# Create DP 2.0
vaddpd ymm1, ymm1, ymm1
# Create DP 0.5
vdivpd ymm2, ymm0, ymm1
loop:
inc i
INSTR ymm0, ymm1, ymm0
INSTR ymm1, ymm0, ymm0
INSTR ymm0, ymm1, ymm0
INSTR ymm1, ymm0, ymm0
INSTR ymm0, ymm1, ymm0
INSTR ymm1, ymm0, ymm0
INSTR ymm0, ymm1, ymm0
INSTR ymm1, ymm0, ymm0
INSTR ymm0, ymm1, ymm0
INSTR ymm1, ymm0, ymm0
INSTR ymm0, ymm1, ymm0
INSTR ymm1, ymm0, ymm0
INSTR ymm0, ymm1, ymm0
INSTR ymm1, ymm0, ymm0
INSTR ymm0, ymm1, ymm0
INSTR ymm1, ymm0, ymm0
INSTR ymm0, ymm1, ymm0
INSTR ymm1, ymm0, ymm0
INSTR ymm0, ymm1, ymm0
INSTR ymm1, ymm0, ymm0
INSTR ymm0, ymm1, ymm0
INSTR ymm1, ymm0, ymm0
INSTR ymm0, ymm1, ymm0
INSTR ymm1, ymm0, ymm0
cmp i, N
jl loop
done:
mov rsp, rbp
pop rbp
ret
.size latency, .-latency

View File

@@ -1,65 +0,0 @@
#define INSTR vaddpd
#define NINST 24
#define N edi
#define i r8d
.intel_syntax noprefix
.globl ninst
.data
ninst:
.long NINST
.text
.globl latency
.type latency, @function
.align 32
latency:
push rbp
mov rbp, rsp
xor i, i
test N, N
jle done
# create DP 1.0
vpcmpeqw xmm0, xmm0, xmm0 # all ones
vpsllq xmm0, xmm0, 54 # logical left shift: 11111110..0 (54=64-(10-1))
vpsrlq xmm0, xmm0, 2 # logical right shift: 1 bit for sign; leading mantissa bit is zero
# copy DP 1.0
vmovaps xmm0, xmm0
vmovaps xmm1, xmm0
# Create DP 2.0
vaddpd xmm1, xmm1, xmm1
# Create DP 0.5
vdivpd xmm2, xmm0, xmm1
loop:
inc i
INSTR xmm3, xmm0, xmm0
INSTR xmm4, xmm1, xmm1
INSTR xmm5, xmm2, xmm2
INSTR xmm3, xmm0, xmm0
INSTR xmm4, xmm1, xmm1
INSTR xmm5, xmm2, xmm2
INSTR xmm6, xmm0, xmm0
INSTR xmm7, xmm1, xmm1
INSTR xmm8, xmm2, xmm2
INSTR xmm9, xmm0, xmm0
INSTR xmm10, xmm1, xmm1
INSTR xmm11, xmm2, xmm2
INSTR xmm12, xmm0, xmm0
INSTR xmm13, xmm1, xmm1
INSTR xmm14, xmm2, xmm2
INSTR xmm15, xmm0, xmm0
INSTR xmm16, xmm1, xmm1
INSTR xmm17, xmm2, xmm2
INSTR xmm18, xmm0, xmm0
INSTR xmm19, xmm1, xmm1
INSTR xmm20, xmm2, xmm2
INSTR xmm21, xmm0, xmm0
INSTR xmm22, xmm1, xmm1
INSTR xmm23, xmm2, xmm2
cmp i, N
jl loop
done:
mov rsp, rbp
pop rbp
ret
.size latency, .-latency

View File

@@ -1,65 +0,0 @@
#define INSTR vaddpd
#define NINST 24
#define N edi
#define i r8d
.intel_syntax noprefix
.globl ninst
.data
ninst:
.long NINST
.text
.globl latency
.type latency, @function
.align 32
latency:
push rbp
mov rbp, rsp
xor i, i
test N, N
jle done
# create DP 1.0
vpcmpeqw xmm0, xmm0, xmm0 # all ones
vpsllq xmm0, xmm0, 54 # logical left shift: 11111110..0 (54=64-(10-1))
vpsrlq xmm0, xmm0, 2 # logical right shift: 1 bit for sign; leading mantissa bit is zero
# copy DP 1.0
vmovaps xmm0, xmm0
vmovaps xmm1, xmm0
# Create DP 2.0
vaddpd xmm1, xmm1, xmm1
# Create DP 0.5
vdivpd xmm2, xmm0, xmm1
loop:
inc i
INSTR xmm0, xmm1, xmm0
INSTR xmm1, xmm0, xmm0
INSTR xmm0, xmm1, xmm0
INSTR xmm1, xmm0, xmm0
INSTR xmm0, xmm1, xmm0
INSTR xmm1, xmm0, xmm0
INSTR xmm0, xmm1, xmm0
INSTR xmm1, xmm0, xmm0
INSTR xmm0, xmm1, xmm0
INSTR xmm1, xmm0, xmm0
INSTR xmm0, xmm1, xmm0
INSTR xmm1, xmm0, xmm0
INSTR xmm0, xmm1, xmm0
INSTR xmm1, xmm0, xmm0
INSTR xmm0, xmm1, xmm0
INSTR xmm1, xmm0, xmm0
INSTR xmm0, xmm1, xmm0
INSTR xmm1, xmm0, xmm0
INSTR xmm0, xmm1, xmm0
INSTR xmm1, xmm0, xmm0
INSTR xmm0, xmm1, xmm0
INSTR xmm1, xmm0, xmm0
INSTR xmm0, xmm1, xmm0
INSTR xmm1, xmm0, xmm0
cmp i, N
jl loop
done:
mov rsp, rbp
pop rbp
ret
.size latency, .-latency

View File

@@ -1,65 +0,0 @@
#define INSTR vaddsd
#define NINST 24
#define N edi
#define i r8d
.intel_syntax noprefix
.globl ninst
.data
ninst:
.long NINST
.text
.globl latency
.type latency, @function
.align 32
latency:
push rbp
mov rbp, rsp
xor i, i
test N, N
jle done
# create DP 1.0
vpcmpeqw xmm0, xmm0, xmm0 # all ones
vpsllq xmm0, xmm0, 54 # logical left shift: 11111110..0 (54=64-(10-1))
vpsrlq xmm0, xmm0, 2 # logical right shift: 1 bit for sign; leading mantissa bit is zero
# copy DP 1.0
vmovaps xmm0, xmm0
vmovaps xmm1, xmm0
# Create DP 2.0
vaddpd xmm1, xmm1, xmm1
# Create DP 0.5
vdivpd xmm2, xmm0, xmm1
loop:
inc i
INSTR xmm3, xmm0, xmm0
INSTR xmm4, xmm1, xmm1
INSTR xmm5, xmm2, xmm2
INSTR xmm3, xmm0, xmm0
INSTR xmm4, xmm1, xmm1
INSTR xmm5, xmm2, xmm2
INSTR xmm6, xmm0, xmm0
INSTR xmm7, xmm1, xmm1
INSTR xmm8, xmm2, xmm2
INSTR xmm9, xmm0, xmm0
INSTR xmm10, xmm1, xmm1
INSTR xmm11, xmm2, xmm2
INSTR xmm12, xmm0, xmm0
INSTR xmm13, xmm1, xmm1
INSTR xmm14, xmm2, xmm2
INSTR xmm15, xmm0, xmm0
INSTR xmm16, xmm1, xmm1
INSTR xmm17, xmm2, xmm2
INSTR xmm18, xmm0, xmm0
INSTR xmm19, xmm1, xmm1
INSTR xmm20, xmm2, xmm2
INSTR xmm21, xmm0, xmm0
INSTR xmm22, xmm1, xmm1
INSTR xmm23, xmm2, xmm2
cmp i, N
jl loop
done:
mov rsp, rbp
pop rbp
ret
.size latency, .-latency

View File

@@ -1,65 +0,0 @@
#define INSTR vaddsd
#define NINST 24
#define N edi
#define i r8d
.intel_syntax noprefix
.globl ninst
.data
ninst:
.long NINST
.text
.globl latency
.type latency, @function
.align 32
latency:
push rbp
mov rbp, rsp
xor i, i
test N, N
jle done
# create DP 1.0
vpcmpeqw xmm0, xmm0, xmm0 # all ones
vpsllq xmm0, xmm0, 54 # logical left shift: 11111110..0 (54=64-(10-1))
vpsrlq xmm0, xmm0, 2 # logical right shift: 1 bit for sign; leading mantissa bit is zero
# copy DP 1.0
vmovaps xmm0, xmm0
vmovaps xmm1, xmm0
# Create DP 2.0
vaddpd xmm1, xmm1, xmm1
# Create DP 0.5
vdivpd xmm2, xmm0, xmm1
loop:
inc i
INSTR xmm0, xmm1, xmm0
INSTR xmm1, xmm0, xmm0
INSTR xmm0, xmm1, xmm0
INSTR xmm1, xmm0, xmm0
INSTR xmm0, xmm1, xmm0
INSTR xmm1, xmm0, xmm0
INSTR xmm0, xmm1, xmm0
INSTR xmm1, xmm0, xmm0
INSTR xmm0, xmm1, xmm0
INSTR xmm1, xmm0, xmm0
INSTR xmm0, xmm1, xmm0
INSTR xmm1, xmm0, xmm0
INSTR xmm0, xmm1, xmm0
INSTR xmm1, xmm0, xmm0
INSTR xmm0, xmm1, xmm0
INSTR xmm1, xmm0, xmm0
INSTR xmm0, xmm1, xmm0
INSTR xmm1, xmm0, xmm0
INSTR xmm0, xmm1, xmm0
INSTR xmm1, xmm0, xmm0
INSTR xmm0, xmm1, xmm0
INSTR xmm1, xmm0, xmm0
INSTR xmm0, xmm1, xmm0
INSTR xmm1, xmm0, xmm0
cmp i, N
jl loop
done:
mov rsp, rbp
pop rbp
ret
.size latency, .-latency

View File

@@ -1,67 +0,0 @@
#define INSTR vmovapd
#define NINST 24
#define N edi
#define i r8d
.intel_syntax noprefix
.globl ninst
.data
ninst:
.long NINST
.text
.globl latency
.type latency, @function
.align 32
latency:
push rbp
mov rbp, rsp
xor i, i
test N, N
jle done
# create DP 1.0
vpcmpeqw xmm0, xmm0, xmm0 # all ones
vpsllq xmm0, xmm0, 54 # logical left shift: 11111110..0 (54=64-(10-1))
vpsrlq xmm0, xmm0, 2 # logical right shift: 1 bit for sign; leading mantissa bit is zero
# expand from SSE to AVX
vinsertf128 ymm0, ymm0, xmm0, 0x1
# copy DP 1.0
vmovaps ymm0, ymm0
vmovaps ymm1, ymm0
# Create DP 2.0
vaddpd ymm1, ymm1, ymm1
# Create DP 0.5
vdivpd ymm2, ymm0, ymm1
loop:
inc i
INSTR ymm3, ymm0
INSTR ymm4, ymm1
INSTR ymm5, ymm2
INSTR ymm3, ymm0
INSTR ymm4, ymm1
INSTR ymm5, ymm2
INSTR ymm6, ymm0
INSTR ymm7, ymm1
INSTR ymm8, ymm2
INSTR ymm9, ymm0
INSTR ymm10, ymm1
INSTR ymm11, ymm2
INSTR ymm12, ymm0
INSTR ymm13, ymm1
INSTR ymm14, ymm2
INSTR ymm15, ymm0
INSTR ymm16, ymm1
INSTR ymm17, ymm2
INSTR ymm18, ymm0
INSTR ymm19, ymm1
INSTR ymm20, ymm2
INSTR ymm21, ymm0
INSTR ymm22, ymm1
INSTR ymm23, ymm2
cmp i, N
jl loop
done:
mov rsp, rbp
pop rbp
ret
.size latency, .-latency

View File

@@ -1,67 +0,0 @@
#define INSTR vmovapd
#define NINST 24
#define N edi
#define i r8d
.intel_syntax noprefix
.globl ninst
.data
ninst:
.long NINST
.text
.globl latency
.type latency, @function
.align 32
latency:
push rbp
mov rbp, rsp
xor i, i
test N, N
jle done
# create DP 1.0
vpcmpeqw xmm0, xmm0, xmm0 # all ones
vpsllq xmm0, xmm0, 54 # logical left shift: 11111110..0 (54=64-(10-1))
vpsrlq xmm0, xmm0, 2 # logical right shift: 1 bit for sign; leading mantissa bit is zero
# expand from SSE to AVX
vinsertf128 ymm0, ymm0, xmm0, 0x1
# copy DP 1.0
vmovaps ymm0, ymm0
vmovaps ymm1, ymm0
# Create DP 2.0
vaddpd ymm1, ymm1, ymm1
# Create DP 0.5
vdivpd ymm2, ymm0, ymm1
loop:
inc i
INSTR ymm0, ymm1
INSTR ymm1, ymm0
INSTR ymm0, ymm1
INSTR ymm1, ymm0
INSTR ymm0, ymm1
INSTR ymm1, ymm0
INSTR ymm0, ymm1
INSTR ymm1, ymm0
INSTR ymm0, ymm1
INSTR ymm1, ymm0
INSTR ymm0, ymm1
INSTR ymm1, ymm0
INSTR ymm0, ymm1
INSTR ymm1, ymm0
INSTR ymm0, ymm1
INSTR ymm1, ymm0
INSTR ymm0, ymm1
INSTR ymm1, ymm0
INSTR ymm0, ymm1
INSTR ymm1, ymm0
INSTR ymm0, ymm1
INSTR ymm1, ymm0
INSTR ymm0, ymm1
INSTR ymm1, ymm0
cmp i, N
jl loop
done:
mov rsp, rbp
pop rbp
ret
.size latency, .-latency

View File

@@ -1,65 +0,0 @@
#define INSTR vmovapd
#define NINST 24
#define N edi
#define i r8d
.intel_syntax noprefix
.globl ninst
.data
ninst:
.long NINST
.text
.globl latency
.type latency, @function
.align 32
latency:
push rbp
mov rbp, rsp
xor i, i
test N, N
jle done
# create DP 1.0
vpcmpeqw xmm0, xmm0, xmm0 # all ones
vpsllq xmm0, xmm0, 54 # logical left shift: 11111110..0 (54=64-(10-1))
vpsrlq xmm0, xmm0, 2 # logical right shift: 1 bit for sign; leading mantissa bit is zero
# copy DP 1.0
vmovaps xmm0, xmm0
vmovaps xmm1, xmm0
# Create DP 2.0
vaddpd xmm1, xmm1, xmm1
# Create DP 0.5
vdivpd xmm2, xmm0, xmm1
loop:
inc i
INSTR xmm3, xmm0
INSTR xmm4, xmm1
INSTR xmm5, xmm2
INSTR xmm3, xmm0
INSTR xmm4, xmm1
INSTR xmm5, xmm2
INSTR xmm6, xmm0
INSTR xmm7, xmm1
INSTR xmm8, xmm2
INSTR xmm9, xmm0
INSTR xmm10, xmm1
INSTR xmm11, xmm2
INSTR xmm12, xmm0
INSTR xmm13, xmm1
INSTR xmm14, xmm2
INSTR xmm15, xmm0
INSTR xmm16, xmm1
INSTR xmm17, xmm2
INSTR xmm18, xmm0
INSTR xmm19, xmm1
INSTR xmm20, xmm2
INSTR xmm21, xmm0
INSTR xmm22, xmm1
INSTR xmm23, xmm2
cmp i, N
jl loop
done:
mov rsp, rbp
pop rbp
ret
.size latency, .-latency

View File

@@ -1,65 +0,0 @@
#define INSTR vmovapd
#define NINST 24
#define N edi
#define i r8d
.intel_syntax noprefix
.globl ninst
.data
ninst:
.long NINST
.text
.globl latency
.type latency, @function
.align 32
latency:
push rbp
mov rbp, rsp
xor i, i
test N, N
jle done
# create DP 1.0
vpcmpeqw xmm0, xmm0, xmm0 # all ones
vpsllq xmm0, xmm0, 54 # logical left shift: 11111110..0 (54=64-(10-1))
vpsrlq xmm0, xmm0, 2 # logical right shift: 1 bit for sign; leading mantissa bit is zero
# copy DP 1.0
vmovaps xmm0, xmm0
vmovaps xmm1, xmm0
# Create DP 2.0
vaddpd xmm1, xmm1, xmm1
# Create DP 0.5
vdivpd xmm2, xmm0, xmm1
loop:
inc i
INSTR xmm0, xmm1
INSTR xmm1, xmm0
INSTR xmm0, xmm1
INSTR xmm1, xmm0
INSTR xmm0, xmm1
INSTR xmm1, xmm0
INSTR xmm0, xmm1
INSTR xmm1, xmm0
INSTR xmm0, xmm1
INSTR xmm1, xmm0
INSTR xmm0, xmm1
INSTR xmm1, xmm0
INSTR xmm0, xmm1
INSTR xmm1, xmm0
INSTR xmm0, xmm1
INSTR xmm1, xmm0
INSTR xmm0, xmm1
INSTR xmm1, xmm0
INSTR xmm0, xmm1
INSTR xmm1, xmm0
INSTR xmm0, xmm1
INSTR xmm1, xmm0
INSTR xmm0, xmm1
INSTR xmm1, xmm0
cmp i, N
jl loop
done:
mov rsp, rbp
pop rbp
ret
.size latency, .-latency

View File

@@ -1,65 +0,0 @@
#define INSTR vmovaps
#define NINST 24
#define N edi
#define i r8d
.intel_syntax noprefix
.globl ninst
.data
ninst:
.long NINST
.text
.globl latency
.type latency, @function
.align 32
latency:
push rbp
mov rbp, rsp
xor i, i
test N, N
jle done
# create DP 1.0
vpcmpeqw xmm0, xmm0, xmm0 # all ones
vpsllq xmm0, xmm0, 54 # logical left shift: 11111110..0 (54=64-(10-1))
vpsrlq xmm0, xmm0, 2 # logical right shift: 1 bit for sign; leading mantissa bit is zero
# copy DP 1.0
vmovaps xmm0, xmm0
vmovaps xmm1, xmm0
# Create DP 2.0
vaddpd xmm1, xmm1, xmm1
# Create DP 0.5
vdivpd xmm2, xmm0, xmm1
loop:
inc i
INSTR xmm3, xmm0
INSTR xmm4, xmm1
INSTR xmm5, xmm2
INSTR xmm3, xmm0
INSTR xmm4, xmm1
INSTR xmm5, xmm2
INSTR xmm6, xmm0
INSTR xmm7, xmm1
INSTR xmm8, xmm2
INSTR xmm9, xmm0
INSTR xmm10, xmm1
INSTR xmm11, xmm2
INSTR xmm12, xmm0
INSTR xmm13, xmm1
INSTR xmm14, xmm2
INSTR xmm15, xmm0
INSTR xmm16, xmm1
INSTR xmm17, xmm2
INSTR xmm18, xmm0
INSTR xmm19, xmm1
INSTR xmm20, xmm2
INSTR xmm21, xmm0
INSTR xmm22, xmm1
INSTR xmm23, xmm2
cmp i, N
jl loop
done:
mov rsp, rbp
pop rbp
ret
.size latency, .-latency

View File

@@ -1,65 +0,0 @@
#define INSTR vmovaps
#define NINST 24
#define N edi
#define i r8d
.intel_syntax noprefix
.globl ninst
.data
ninst:
.long NINST
.text
.globl latency
.type latency, @function
.align 32
latency:
push rbp
mov rbp, rsp
xor i, i
test N, N
jle done
# create DP 1.0
vpcmpeqw xmm0, xmm0, xmm0 # all ones
vpsllq xmm0, xmm0, 54 # logical left shift: 11111110..0 (54=64-(10-1))
vpsrlq xmm0, xmm0, 2 # logical right shift: 1 bit for sign; leading mantissa bit is zero
# copy DP 1.0
vmovaps xmm0, xmm0
vmovaps xmm1, xmm0
# Create DP 2.0
vaddpd xmm1, xmm1, xmm1
# Create DP 0.5
vdivpd xmm2, xmm0, xmm1
loop:
inc i
INSTR xmm0, xmm1
INSTR xmm1, xmm0
INSTR xmm0, xmm1
INSTR xmm1, xmm0
INSTR xmm0, xmm1
INSTR xmm1, xmm0
INSTR xmm0, xmm1
INSTR xmm1, xmm0
INSTR xmm0, xmm1
INSTR xmm1, xmm0
INSTR xmm0, xmm1
INSTR xmm1, xmm0
INSTR xmm0, xmm1
INSTR xmm1, xmm0
INSTR xmm0, xmm1
INSTR xmm1, xmm0
INSTR xmm0, xmm1
INSTR xmm1, xmm0
INSTR xmm0, xmm1
INSTR xmm1, xmm0
INSTR xmm0, xmm1
INSTR xmm1, xmm0
INSTR xmm0, xmm1
INSTR xmm1, xmm0
cmp i, N
jl loop
done:
mov rsp, rbp
pop rbp
ret
.size latency, .-latency

View File

@@ -1,98 +0,0 @@
#define INSTR vmovq
#define NINST 24
#define N edi
#define i r8d
.intel_syntax noprefix
.globl ninst
.data
ninst:
.long NINST
.text
.globl latency
.type latency, @function
.align 32
latency:
push rbp
mov rbp, rsp
xor i, i
test N, N
jle done
# create DP 1.0
vpcmpeqw xmm0, xmm0, xmm0 # all ones
vpsllq xmm0, xmm0, 54 # logical left shift: 11111110..0 (54=64-(10-1))
vpsrlq xmm0, xmm0, 2 # logical right shift: 1 bit for sign; leading mantissa bit is zero
push rax
push rbx
push rcx
push rdx
push r9
push r10
push r11
push r12
push r13
push r14
push r15
xor rax, rax
xor rbx, rbx
xor rcx, rcx
xor rdx, rdx
xor r9, r9
xor r10, r10
xor r11, r11
xor r12, r12
xor r13, r13
xor r14, r14
xor r15, r15
# copy DP 1.0
vmovaps xmm0, xmm0
vmovaps xmm1, xmm0
# Create DP 2.0
vaddpd xmm1, xmm1, xmm1
# Create DP 0.5
vdivpd xmm2, xmm0, xmm1
loop:
inc i
INSTR rdx, xmm0
INSTR r9, xmm1
INSTR r10, xmm2
INSTR rdx, xmm0
INSTR r9, xmm1
INSTR r10, xmm2
INSTR r11, xmm0
INSTR r12, xmm1
INSTR r13, xmm2
INSTR r14, xmm0
INSTR r15, xmm1
INSTR rax, xmm2
INSTR rbx, xmm0
INSTR rcx, xmm1
INSTR rdx, xmm2
INSTR r9, xmm0
INSTR r10, xmm1
INSTR r11, xmm2
INSTR r12, xmm0
INSTR r13, xmm1
INSTR r14, xmm2
INSTR r15, xmm0
INSTR rax, xmm1
INSTR rbx, xmm2
cmp i, N
jl loop
pop r15
pop r14
pop r13
pop r12
pop r11
pop r10
pop r9
pop rdx
pop rcx
pop rbx
pop rax
done:
mov rsp, rbp
pop rbp
ret
.size latency, .-latency

View File

@@ -1,98 +0,0 @@
#define INSTR vmovq
#define NINST 24
#define N edi
#define i r8d
.intel_syntax noprefix
.globl ninst
.data
ninst:
.long NINST
.text
.globl latency
.type latency, @function
.align 32
latency:
push rbp
mov rbp, rsp
xor i, i
test N, N
jle done
# create DP 1.0
vpcmpeqw xmm0, xmm0, xmm0 # all ones
vpsllq xmm0, xmm0, 54 # logical left shift: 11111110..0 (54=64-(10-1))
vpsrlq xmm0, xmm0, 2 # logical right shift: 1 bit for sign; leading mantissa bit is zero
push rax
push rbx
push rcx
push rdx
push r9
push r10
push r11
push r12
push r13
push r14
push r15
xor rax, rax
xor rbx, rbx
xor rcx, rcx
xor rdx, rdx
xor r9, r9
xor r10, r10
xor r11, r11
xor r12, r12
xor r13, r13
xor r14, r14
xor r15, r15
# copy DP 1.0
vmovaps xmm0, xmm0
vmovaps xmm1, xmm0
# Create DP 2.0
vaddpd xmm1, xmm1, xmm1
# Create DP 0.5
vdivpd xmm2, xmm0, xmm1
loop:
inc i
INSTR rax, xmm0
INSTR rax, xmm0
INSTR rax, xmm0
INSTR rax, xmm0
INSTR rax, xmm0
INSTR rax, xmm0
INSTR rax, xmm0
INSTR rax, xmm0
INSTR rax, xmm0
INSTR rax, xmm0
INSTR rax, xmm0
INSTR rax, xmm0
INSTR rax, xmm0
INSTR rax, xmm0
INSTR rax, xmm0
INSTR rax, xmm0
INSTR rax, xmm0
INSTR rax, xmm0
INSTR rax, xmm0
INSTR rax, xmm0
INSTR rax, xmm0
INSTR rax, xmm0
INSTR rax, xmm0
INSTR rax, xmm0
cmp i, N
jl loop
pop r15
pop r14
pop r13
pop r12
pop r11
pop r10
pop r9
pop rdx
pop rcx
pop rbx
pop rax
done:
mov rsp, rbp
pop rbp
ret
.size latency, .-latency

View File

@@ -1,100 +0,0 @@
#define INSTR vmovq
#define NINST 24
#define N edi
#define i r8d
.intel_syntax noprefix
.globl ninst
.data
ninst:
.long NINST
.text
.globl latency
.type latency, @function
.align 32
latency:
push rbp
mov rbp, rsp
xor i, i
test N, N
jle done
# create DP 1.0
vpcmpeqw xmm0, xmm0, xmm0 # all ones
vpsllq xmm0, xmm0, 54 # logical left shift: 11111110..0 (54=64-(10-1))
vpsrlq xmm0, xmm0, 2 # logical right shift: 1 bit for sign; leading mantissa bit is zero
push rax
push rbx
push rcx
push rdx
push r9
push r10
push r11
push r12
push r13
push r14
push r15
xor rax, rax
xor rbx, rbx
xor rcx, rcx
xor rdx, rdx
xor r9, r9
xor r10, r10
xor r11, r11
xor r12, r12
xor r13, r13
xor r14, r14
xor r15, r15
# copy DP 1.0
vmovq rax, xmm0
vmovq rbx, xmm0
# Create DP 2.0
add rbx, rax
# Create DP 0.5
div rax
movq rcx, rax
vmovq rax, xmm0
loop:
inc i
INSTR xmm3, rax
INSTR xmm4, rbx
INSTR xmm5, rcx
INSTR xmm3, rax
INSTR xmm4, rbx
INSTR xmm5, rcx
INSTR xmm6, rax
INSTR xmm7, rbx
INSTR xmm8, rcx
INSTR xmm9, rax
INSTR xmm10, rbx
INSTR xmm11, rcx
INSTR xmm12, rax
INSTR xmm13, rbx
INSTR xmm14, rcx
INSTR xmm15, rax
INSTR xmm16, rbx
INSTR xmm17, rcx
INSTR xmm18, rax
INSTR xmm19, rbx
INSTR xmm20, rcx
INSTR xmm21, rax
INSTR xmm22, rbx
INSTR xmm23, rcx
cmp i, N
jl loop
pop r15
pop r14
pop r13
pop r12
pop r11
pop r10
pop r9
pop rdx
pop rcx
pop rbx
pop rax
done:
mov rsp, rbp
pop rbp
ret
.size latency, .-latency

View File

@@ -1,100 +0,0 @@
#define INSTR vmovq
#define NINST 24
#define N edi
#define i r8d
.intel_syntax noprefix
.globl ninst
.data
ninst:
.long NINST
.text
.globl latency
.type latency, @function
.align 32
latency:
push rbp
mov rbp, rsp
xor i, i
test N, N
jle done
# create DP 1.0
vpcmpeqw xmm0, xmm0, xmm0 # all ones
vpsllq xmm0, xmm0, 54 # logical left shift: 11111110..0 (54=64-(10-1))
vpsrlq xmm0, xmm0, 2 # logical right shift: 1 bit for sign; leading mantissa bit is zero
push rax
push rbx
push rcx
push rdx
push r9
push r10
push r11
push r12
push r13
push r14
push r15
xor rax, rax
xor rbx, rbx
xor rcx, rcx
xor rdx, rdx
xor r9, r9
xor r10, r10
xor r11, r11
xor r12, r12
xor r13, r13
xor r14, r14
xor r15, r15
# copy DP 1.0
vmovq rax, xmm0
vmovq rbx, xmm0
# Create DP 2.0
add rbx, rax
# Create DP 0.5
div rax
movq rcx, rax
vmovq rax, xmm0
loop:
inc i
INSTR xmm0, rax
INSTR xmm0, rax
INSTR xmm0, rax
INSTR xmm0, rax
INSTR xmm0, rax
INSTR xmm0, rax
INSTR xmm0, rax
INSTR xmm0, rax
INSTR xmm0, rax
INSTR xmm0, rax
INSTR xmm0, rax
INSTR xmm0, rax
INSTR xmm0, rax
INSTR xmm0, rax
INSTR xmm0, rax
INSTR xmm0, rax
INSTR xmm0, rax
INSTR xmm0, rax
INSTR xmm0, rax
INSTR xmm0, rax
INSTR xmm0, rax
INSTR xmm0, rax
INSTR xmm0, rax
INSTR xmm0, rax
cmp i, N
jl loop
pop r15
pop r14
pop r13
pop r12
pop r11
pop r10
pop r9
pop rdx
pop rcx
pop rbx
pop rax
done:
mov rsp, rbp
pop rbp
ret
.size latency, .-latency

View File

@@ -1,65 +0,0 @@
#define INSTR vmovsd
#define NINST 24
#define N edi
#define i r8d
.intel_syntax noprefix
.globl ninst
.data
ninst:
.long NINST
.text
.globl latency
.type latency, @function
.align 32
latency:
push rbp
mov rbp, rsp
xor i, i
test N, N
jle done
# create DP 1.0
vpcmpeqw xmm0, xmm0, xmm0 # all ones
vpsllq xmm0, xmm0, 54 # logical left shift: 11111110..0 (54=64-(10-1))
vpsrlq xmm0, xmm0, 2 # logical right shift: 1 bit for sign; leading mantissa bit is zero
# copy DP 1.0
vmovaps xmm0, xmm0
vmovaps xmm1, xmm0
# Create DP 2.0
vaddpd xmm1, xmm1, xmm1
# Create DP 0.5
vdivpd xmm2, xmm0, xmm1
loop:
inc i
INSTR xmm3, xmm0, xmm0
INSTR xmm4, xmm1, xmm1
INSTR xmm5, xmm2, xmm2
INSTR xmm3, xmm0, xmm0
INSTR xmm4, xmm1, xmm1
INSTR xmm5, xmm2, xmm2
INSTR xmm6, xmm0, xmm0
INSTR xmm7, xmm1, xmm1
INSTR xmm8, xmm2, xmm2
INSTR xmm9, xmm0, xmm0
INSTR xmm10, xmm1, xmm1
INSTR xmm11, xmm2, xmm2
INSTR xmm12, xmm0, xmm0
INSTR xmm13, xmm1, xmm1
INSTR xmm14, xmm2, xmm2
INSTR xmm15, xmm0, xmm0
INSTR xmm16, xmm1, xmm1
INSTR xmm17, xmm2, xmm2
INSTR xmm18, xmm0, xmm0
INSTR xmm19, xmm1, xmm1
INSTR xmm20, xmm2, xmm2
INSTR xmm21, xmm0, xmm0
INSTR xmm22, xmm1, xmm1
INSTR xmm23, xmm2, xmm2
cmp i, N
jl loop
done:
mov rsp, rbp
pop rbp
ret
.size latency, .-latency

View File

@@ -1,65 +0,0 @@
#define INSTR vmovsd
#define NINST 24
#define N edi
#define i r8d
.intel_syntax noprefix
.globl ninst
.data
ninst:
.long NINST
.text
.globl latency
.type latency, @function
.align 32
latency:
push rbp
mov rbp, rsp
xor i, i
test N, N
jle done
# create DP 1.0
vpcmpeqw xmm0, xmm0, xmm0 # all ones
vpsllq xmm0, xmm0, 54 # logical left shift: 11111110..0 (54=64-(10-1))
vpsrlq xmm0, xmm0, 2 # logical right shift: 1 bit for sign; leading mantissa bit is zero
# copy DP 1.0
vmovaps xmm0, xmm0
vmovaps xmm1, xmm0
# Create DP 2.0
vaddpd xmm1, xmm1, xmm1
# Create DP 0.5
vdivpd xmm2, xmm0, xmm1
loop:
inc i
INSTR xmm0, xmm1, xmm0
INSTR xmm1, xmm0, xmm0
INSTR xmm0, xmm1, xmm0
INSTR xmm1, xmm0, xmm0
INSTR xmm0, xmm1, xmm0
INSTR xmm1, xmm0, xmm0
INSTR xmm0, xmm1, xmm0
INSTR xmm1, xmm0, xmm0
INSTR xmm0, xmm1, xmm0
INSTR xmm1, xmm0, xmm0
INSTR xmm0, xmm1, xmm0
INSTR xmm1, xmm0, xmm0
INSTR xmm0, xmm1, xmm0
INSTR xmm1, xmm0, xmm0
INSTR xmm0, xmm1, xmm0
INSTR xmm1, xmm0, xmm0
INSTR xmm0, xmm1, xmm0
INSTR xmm1, xmm0, xmm0
INSTR xmm0, xmm1, xmm0
INSTR xmm1, xmm0, xmm0
INSTR xmm0, xmm1, xmm0
INSTR xmm1, xmm0, xmm0
INSTR xmm0, xmm1, xmm0
INSTR xmm1, xmm0, xmm0
cmp i, N
jl loop
done:
mov rsp, rbp
pop rbp
ret
.size latency, .-latency

View File

@@ -1,67 +0,0 @@
#define INSTR vmulpd
#define NINST 24
#define N edi
#define i r8d
.intel_syntax noprefix
.globl ninst
.data
ninst:
.long NINST
.text
.globl latency
.type latency, @function
.align 32
latency:
push rbp
mov rbp, rsp
xor i, i
test N, N
jle done
# create DP 1.0
vpcmpeqw xmm0, xmm0, xmm0 # all ones
vpsllq xmm0, xmm0, 54 # logical left shift: 11111110..0 (54=64-(10-1))
vpsrlq xmm0, xmm0, 2 # logical right shift: 1 bit for sign; leading mantissa bit is zero
# expand from SSE to AVX
vinsertf128 ymm0, ymm0, xmm0, 0x1
# copy DP 1.0
vmovaps ymm0, ymm0
vmovaps ymm1, ymm0
# Create DP 2.0
vaddpd ymm1, ymm1, ymm1
# Create DP 0.5
vdivpd ymm2, ymm0, ymm1
loop:
inc i
INSTR ymm3, ymm0, ymm0
INSTR ymm4, ymm1, ymm1
INSTR ymm5, ymm2, ymm2
INSTR ymm3, ymm0, ymm0
INSTR ymm4, ymm1, ymm1
INSTR ymm5, ymm2, ymm2
INSTR ymm6, ymm0, ymm0
INSTR ymm7, ymm1, ymm1
INSTR ymm8, ymm2, ymm2
INSTR ymm9, ymm0, ymm0
INSTR ymm10, ymm1, ymm1
INSTR ymm11, ymm2, ymm2
INSTR ymm12, ymm0, ymm0
INSTR ymm13, ymm1, ymm1
INSTR ymm14, ymm2, ymm2
INSTR ymm15, ymm0, ymm0
INSTR ymm16, ymm1, ymm1
INSTR ymm17, ymm2, ymm2
INSTR ymm18, ymm0, ymm0
INSTR ymm19, ymm1, ymm1
INSTR ymm20, ymm2, ymm2
INSTR ymm21, ymm0, ymm0
INSTR ymm22, ymm1, ymm1
INSTR ymm23, ymm2, ymm2
cmp i, N
jl loop
done:
mov rsp, rbp
pop rbp
ret
.size latency, .-latency

View File

@@ -1,67 +0,0 @@
#define INSTR vmulpd
#define NINST 24
#define N edi
#define i r8d
.intel_syntax noprefix
.globl ninst
.data
ninst:
.long NINST
.text
.globl latency
.type latency, @function
.align 32
latency:
push rbp
mov rbp, rsp
xor i, i
test N, N
jle done
# create DP 1.0
vpcmpeqw xmm0, xmm0, xmm0 # all ones
vpsllq xmm0, xmm0, 54 # logical left shift: 11111110..0 (54=64-(10-1))
vpsrlq xmm0, xmm0, 2 # logical right shift: 1 bit for sign; leading mantissa bit is zero
# expand from SSE to AVX
vinsertf128 ymm0, ymm0, xmm0, 0x1
# copy DP 1.0
vmovaps ymm0, ymm0
vmovaps ymm1, ymm0
# Create DP 2.0
vaddpd ymm1, ymm1, ymm1
# Create DP 0.5
vdivpd ymm2, ymm0, ymm1
loop:
inc i
INSTR ymm0, ymm1, ymm0
INSTR ymm1, ymm0, ymm0
INSTR ymm0, ymm1, ymm0
INSTR ymm1, ymm0, ymm0
INSTR ymm0, ymm1, ymm0
INSTR ymm1, ymm0, ymm0
INSTR ymm0, ymm1, ymm0
INSTR ymm1, ymm0, ymm0
INSTR ymm0, ymm1, ymm0
INSTR ymm1, ymm0, ymm0
INSTR ymm0, ymm1, ymm0
INSTR ymm1, ymm0, ymm0
INSTR ymm0, ymm1, ymm0
INSTR ymm1, ymm0, ymm0
INSTR ymm0, ymm1, ymm0
INSTR ymm1, ymm0, ymm0
INSTR ymm0, ymm1, ymm0
INSTR ymm1, ymm0, ymm0
INSTR ymm0, ymm1, ymm0
INSTR ymm1, ymm0, ymm0
INSTR ymm0, ymm1, ymm0
INSTR ymm1, ymm0, ymm0
INSTR ymm0, ymm1, ymm0
INSTR ymm1, ymm0, ymm0
cmp i, N
jl loop
done:
mov rsp, rbp
pop rbp
ret
.size latency, .-latency

View File

@@ -1,65 +0,0 @@
#define INSTR vmulsd
#define NINST 24
#define N edi
#define i r8d
.intel_syntax noprefix
.globl ninst
.data
ninst:
.long NINST
.text
.globl latency
.type latency, @function
.align 32
latency:
push rbp
mov rbp, rsp
xor i, i
test N, N
jle done
# create DP 1.0
vpcmpeqw xmm0, xmm0, xmm0 # all ones
vpsllq xmm0, xmm0, 54 # logical left shift: 11111110..0 (54=64-(10-1))
vpsrlq xmm0, xmm0, 2 # logical right shift: 1 bit for sign; leading mantissa bit is zero
# copy DP 1.0
vmovaps xmm0, xmm0
vmovaps xmm1, xmm0
# Create DP 2.0
vaddpd xmm1, xmm1, xmm1
# Create DP 0.5
vdivpd xmm2, xmm0, xmm1
loop:
inc i
INSTR xmm3, xmm0, xmm0
INSTR xmm4, xmm1, xmm1
INSTR xmm5, xmm2, xmm2
INSTR xmm3, xmm0, xmm0
INSTR xmm4, xmm1, xmm1
INSTR xmm5, xmm2, xmm2
INSTR xmm6, xmm0, xmm0
INSTR xmm7, xmm1, xmm1
INSTR xmm8, xmm2, xmm2
INSTR xmm9, xmm0, xmm0
INSTR xmm10, xmm1, xmm1
INSTR xmm11, xmm2, xmm2
INSTR xmm12, xmm0, xmm0
INSTR xmm13, xmm1, xmm1
INSTR xmm14, xmm2, xmm2
INSTR xmm15, xmm0, xmm0
INSTR xmm16, xmm1, xmm1
INSTR xmm17, xmm2, xmm2
INSTR xmm18, xmm0, xmm0
INSTR xmm19, xmm1, xmm1
INSTR xmm20, xmm2, xmm2
INSTR xmm21, xmm0, xmm0
INSTR xmm22, xmm1, xmm1
INSTR xmm23, xmm2, xmm2
cmp i, N
jl loop
done:
mov rsp, rbp
pop rbp
ret
.size latency, .-latency

View File

@@ -1,65 +0,0 @@
#define INSTR vmulsd
#define NINST 24
#define N edi
#define i r8d
.intel_syntax noprefix
.globl ninst
.data
ninst:
.long NINST
.text
.globl latency
.type latency, @function
.align 32
latency:
push rbp
mov rbp, rsp
xor i, i
test N, N
jle done
# create DP 1.0
vpcmpeqw xmm0, xmm0, xmm0 # all ones
vpsllq xmm0, xmm0, 54 # logical left shift: 11111110..0 (54=64-(10-1))
vpsrlq xmm0, xmm0, 2 # logical right shift: 1 bit for sign; leading mantissa bit is zero
# copy DP 1.0
vmovaps xmm0, xmm0
vmovaps xmm1, xmm0
# Create DP 2.0
vaddpd xmm1, xmm1, xmm1
# Create DP 0.5
vdivpd xmm2, xmm0, xmm1
loop:
inc i
INSTR xmm0, xmm1, xmm0
INSTR xmm1, xmm0, xmm0
INSTR xmm0, xmm1, xmm0
INSTR xmm1, xmm0, xmm0
INSTR xmm0, xmm1, xmm0
INSTR xmm1, xmm0, xmm0
INSTR xmm0, xmm1, xmm0
INSTR xmm1, xmm0, xmm0
INSTR xmm0, xmm1, xmm0
INSTR xmm1, xmm0, xmm0
INSTR xmm0, xmm1, xmm0
INSTR xmm1, xmm0, xmm0
INSTR xmm0, xmm1, xmm0
INSTR xmm1, xmm0, xmm0
INSTR xmm0, xmm1, xmm0
INSTR xmm1, xmm0, xmm0
INSTR xmm0, xmm1, xmm0
INSTR xmm1, xmm0, xmm0
INSTR xmm0, xmm1, xmm0
INSTR xmm1, xmm0, xmm0
INSTR xmm0, xmm1, xmm0
INSTR xmm1, xmm0, xmm0
INSTR xmm0, xmm1, xmm0
INSTR xmm1, xmm0, xmm0
cmp i, N
jl loop
done:
mov rsp, rbp
pop rbp
ret
.size latency, .-latency

View File

@@ -1,67 +0,0 @@
#define INSTR vsubpd
#define NINST 24
#define N edi
#define i r8d
.intel_syntax noprefix
.globl ninst
.data
ninst:
.long NINST
.text
.globl latency
.type latency, @function
.align 32
latency:
push rbp
mov rbp, rsp
xor i, i
test N, N
jle done
# create DP 1.0
vpcmpeqw xmm0, xmm0, xmm0 # all ones
vpsllq xmm0, xmm0, 54 # logical left shift: 11111110..0 (54=64-(10-1))
vpsrlq xmm0, xmm0, 2 # logical right shift: 1 bit for sign; leading mantissa bit is zero
# expand from SSE to AVX
vinsertf128 ymm0, ymm0, xmm0, 0x1
# copy DP 1.0
vmovaps ymm0, ymm0
vmovaps ymm1, ymm0
# Create DP 2.0
vaddpd ymm1, ymm1, ymm1
# Create DP 0.5
vdivpd ymm2, ymm0, ymm1
loop:
inc i
INSTR ymm3, ymm0, ymm0
INSTR ymm4, ymm1, ymm1
INSTR ymm5, ymm2, ymm2
INSTR ymm3, ymm0, ymm0
INSTR ymm4, ymm1, ymm1
INSTR ymm5, ymm2, ymm2
INSTR ymm6, ymm0, ymm0
INSTR ymm7, ymm1, ymm1
INSTR ymm8, ymm2, ymm2
INSTR ymm9, ymm0, ymm0
INSTR ymm10, ymm1, ymm1
INSTR ymm11, ymm2, ymm2
INSTR ymm12, ymm0, ymm0
INSTR ymm13, ymm1, ymm1
INSTR ymm14, ymm2, ymm2
INSTR ymm15, ymm0, ymm0
INSTR ymm16, ymm1, ymm1
INSTR ymm17, ymm2, ymm2
INSTR ymm18, ymm0, ymm0
INSTR ymm19, ymm1, ymm1
INSTR ymm20, ymm2, ymm2
INSTR ymm21, ymm0, ymm0
INSTR ymm22, ymm1, ymm1
INSTR ymm23, ymm2, ymm2
cmp i, N
jl loop
done:
mov rsp, rbp
pop rbp
ret
.size latency, .-latency

View File

@@ -1,67 +0,0 @@
#define INSTR vsubpd
#define NINST 24
#define N edi
#define i r8d
.intel_syntax noprefix
.globl ninst
.data
ninst:
.long NINST
.text
.globl latency
.type latency, @function
.align 32
latency:
push rbp
mov rbp, rsp
xor i, i
test N, N
jle done
# create DP 1.0
vpcmpeqw xmm0, xmm0, xmm0 # all ones
vpsllq xmm0, xmm0, 54 # logical left shift: 11111110..0 (54=64-(10-1))
vpsrlq xmm0, xmm0, 2 # logical right shift: 1 bit for sign; leading mantissa bit is zero
# expand from SSE to AVX
vinsertf128 ymm0, ymm0, xmm0, 0x1
# copy DP 1.0
vmovaps ymm0, ymm0
vmovaps ymm1, ymm0
# Create DP 2.0
vaddpd ymm1, ymm1, ymm1
# Create DP 0.5
vdivpd ymm2, ymm0, ymm1
loop:
inc i
INSTR ymm0, ymm1, ymm0
INSTR ymm1, ymm0, ymm0
INSTR ymm0, ymm1, ymm0
INSTR ymm1, ymm0, ymm0
INSTR ymm0, ymm1, ymm0
INSTR ymm1, ymm0, ymm0
INSTR ymm0, ymm1, ymm0
INSTR ymm1, ymm0, ymm0
INSTR ymm0, ymm1, ymm0
INSTR ymm1, ymm0, ymm0
INSTR ymm0, ymm1, ymm0
INSTR ymm1, ymm0, ymm0
INSTR ymm0, ymm1, ymm0
INSTR ymm1, ymm0, ymm0
INSTR ymm0, ymm1, ymm0
INSTR ymm1, ymm0, ymm0
INSTR ymm0, ymm1, ymm0
INSTR ymm1, ymm0, ymm0
INSTR ymm0, ymm1, ymm0
INSTR ymm1, ymm0, ymm0
INSTR ymm0, ymm1, ymm0
INSTR ymm1, ymm0, ymm0
INSTR ymm0, ymm1, ymm0
INSTR ymm1, ymm0, ymm0
cmp i, N
jl loop
done:
mov rsp, rbp
pop rbp
ret
.size latency, .-latency

View File

@@ -1,65 +0,0 @@
#define INSTR vsubsd
#define NINST 24
#define N edi
#define i r8d
.intel_syntax noprefix
.globl ninst
.data
ninst:
.long NINST
.text
.globl latency
.type latency, @function
.align 32
latency:
push rbp
mov rbp, rsp
xor i, i
test N, N
jle done
# create DP 1.0
vpcmpeqw xmm0, xmm0, xmm0 # all ones
vpsllq xmm0, xmm0, 54 # logical left shift: 11111110..0 (54=64-(10-1))
vpsrlq xmm0, xmm0, 2 # logical right shift: 1 bit for sign; leading mantissa bit is zero
# copy DP 1.0
vmovaps xmm0, xmm0
vmovaps xmm1, xmm0
# Create DP 2.0
vaddpd xmm1, xmm1, xmm1
# Create DP 0.5
vdivpd xmm2, xmm0, xmm1
loop:
inc i
INSTR xmm3, xmm0, xmm0
INSTR xmm4, xmm1, xmm1
INSTR xmm5, xmm2, xmm2
INSTR xmm3, xmm0, xmm0
INSTR xmm4, xmm1, xmm1
INSTR xmm5, xmm2, xmm2
INSTR xmm6, xmm0, xmm0
INSTR xmm7, xmm1, xmm1
INSTR xmm8, xmm2, xmm2
INSTR xmm9, xmm0, xmm0
INSTR xmm10, xmm1, xmm1
INSTR xmm11, xmm2, xmm2
INSTR xmm12, xmm0, xmm0
INSTR xmm13, xmm1, xmm1
INSTR xmm14, xmm2, xmm2
INSTR xmm15, xmm0, xmm0
INSTR xmm16, xmm1, xmm1
INSTR xmm17, xmm2, xmm2
INSTR xmm18, xmm0, xmm0
INSTR xmm19, xmm1, xmm1
INSTR xmm20, xmm2, xmm2
INSTR xmm21, xmm0, xmm0
INSTR xmm22, xmm1, xmm1
INSTR xmm23, xmm2, xmm2
cmp i, N
jl loop
done:
mov rsp, rbp
pop rbp
ret
.size latency, .-latency

View File

@@ -1,65 +0,0 @@
#define INSTR vsubsd
#define NINST 24
#define N edi
#define i r8d
.intel_syntax noprefix
.globl ninst
.data
ninst:
.long NINST
.text
.globl latency
.type latency, @function
.align 32
latency:
push rbp
mov rbp, rsp
xor i, i
test N, N
jle done
# create DP 1.0
vpcmpeqw xmm0, xmm0, xmm0 # all ones
vpsllq xmm0, xmm0, 54 # logical left shift: 11111110..0 (54=64-(10-1))
vpsrlq xmm0, xmm0, 2 # logical right shift: 1 bit for sign; leading mantissa bit is zero
# copy DP 1.0
vmovaps xmm0, xmm0
vmovaps xmm1, xmm0
# Create DP 2.0
vaddpd xmm1, xmm1, xmm1
# Create DP 0.5
vdivpd xmm2, xmm0, xmm1
loop:
inc i
INSTR xmm0, xmm1, xmm0
INSTR xmm1, xmm0, xmm0
INSTR xmm0, xmm1, xmm0
INSTR xmm1, xmm0, xmm0
INSTR xmm0, xmm1, xmm0
INSTR xmm1, xmm0, xmm0
INSTR xmm0, xmm1, xmm0
INSTR xmm1, xmm0, xmm0
INSTR xmm0, xmm1, xmm0
INSTR xmm1, xmm0, xmm0
INSTR xmm0, xmm1, xmm0
INSTR xmm1, xmm0, xmm0
INSTR xmm0, xmm1, xmm0
INSTR xmm1, xmm0, xmm0
INSTR xmm0, xmm1, xmm0
INSTR xmm1, xmm0, xmm0
INSTR xmm0, xmm1, xmm0
INSTR xmm1, xmm0, xmm0
INSTR xmm0, xmm1, xmm0
INSTR xmm1, xmm0, xmm0
INSTR xmm0, xmm1, xmm0
INSTR xmm1, xmm0, xmm0
INSTR xmm0, xmm1, xmm0
INSTR xmm1, xmm0, xmm0
cmp i, N
jl loop
done:
mov rsp, rbp
pop rbp
ret
.size latency, .-latency

View File

@@ -1,65 +0,0 @@
#define INSTR vunpckhpd
#define NINST 24
#define N edi
#define i r8d
.intel_syntax noprefix
.globl ninst
.data
ninst:
.long NINST
.text
.globl latency
.type latency, @function
.align 32
latency:
push rbp
mov rbp, rsp
xor i, i
test N, N
jle done
# create DP 1.0
vpcmpeqw xmm0, xmm0, xmm0 # all ones
vpsllq xmm0, xmm0, 54 # logical left shift: 11111110..0 (54=64-(10-1))
vpsrlq xmm0, xmm0, 2 # logical right shift: 1 bit for sign; leading mantissa bit is zero
# copy DP 1.0
vmovaps xmm0, xmm0
vmovaps xmm1, xmm0
# Create DP 2.0
vaddpd xmm1, xmm1, xmm1
# Create DP 0.5
vdivpd xmm2, xmm0, xmm1
loop:
inc i
INSTR xmm3, xmm0, xmm0
INSTR xmm4, xmm1, xmm1
INSTR xmm5, xmm2, xmm2
INSTR xmm3, xmm0, xmm0
INSTR xmm4, xmm1, xmm1
INSTR xmm5, xmm2, xmm2
INSTR xmm6, xmm0, xmm0
INSTR xmm7, xmm1, xmm1
INSTR xmm8, xmm2, xmm2
INSTR xmm9, xmm0, xmm0
INSTR xmm10, xmm1, xmm1
INSTR xmm11, xmm2, xmm2
INSTR xmm12, xmm0, xmm0
INSTR xmm13, xmm1, xmm1
INSTR xmm14, xmm2, xmm2
INSTR xmm15, xmm0, xmm0
INSTR xmm16, xmm1, xmm1
INSTR xmm17, xmm2, xmm2
INSTR xmm18, xmm0, xmm0
INSTR xmm19, xmm1, xmm1
INSTR xmm20, xmm2, xmm2
INSTR xmm21, xmm0, xmm0
INSTR xmm22, xmm1, xmm1
INSTR xmm23, xmm2, xmm2
cmp i, N
jl loop
done:
mov rsp, rbp
pop rbp
ret
.size latency, .-latency

View File

@@ -1,65 +0,0 @@
#define INSTR vunpckhpd
#define NINST 24
#define N edi
#define i r8d
.intel_syntax noprefix
.globl ninst
.data
ninst:
.long NINST
.text
.globl latency
.type latency, @function
.align 32
latency:
push rbp
mov rbp, rsp
xor i, i
test N, N
jle done
# create DP 1.0
vpcmpeqw xmm0, xmm0, xmm0 # all ones
vpsllq xmm0, xmm0, 54 # logical left shift: 11111110..0 (54=64-(10-1))
vpsrlq xmm0, xmm0, 2 # logical right shift: 1 bit for sign; leading mantissa bit is zero
# copy DP 1.0
vmovaps xmm0, xmm0
vmovaps xmm1, xmm0
# Create DP 2.0
vaddpd xmm1, xmm1, xmm1
# Create DP 0.5
vdivpd xmm2, xmm0, xmm1
loop:
inc i
INSTR xmm0, xmm1, xmm0
INSTR xmm1, xmm0, xmm0
INSTR xmm0, xmm1, xmm0
INSTR xmm1, xmm0, xmm0
INSTR xmm0, xmm1, xmm0
INSTR xmm1, xmm0, xmm0
INSTR xmm0, xmm1, xmm0
INSTR xmm1, xmm0, xmm0
INSTR xmm0, xmm1, xmm0
INSTR xmm1, xmm0, xmm0
INSTR xmm0, xmm1, xmm0
INSTR xmm1, xmm0, xmm0
INSTR xmm0, xmm1, xmm0
INSTR xmm1, xmm0, xmm0
INSTR xmm0, xmm1, xmm0
INSTR xmm1, xmm0, xmm0
INSTR xmm0, xmm1, xmm0
INSTR xmm1, xmm0, xmm0
INSTR xmm0, xmm1, xmm0
INSTR xmm1, xmm0, xmm0
INSTR xmm0, xmm1, xmm0
INSTR xmm1, xmm0, xmm0
INSTR xmm0, xmm1, xmm0
INSTR xmm1, xmm0, xmm0
cmp i, N
jl loop
done:
mov rsp, rbp
pop rbp
ret
.size latency, .-latency

View File

@@ -1,67 +0,0 @@
#define INSTR vxorpd
#define NINST 24
#define N edi
#define i r8d
.intel_syntax noprefix
.globl ninst
.data
ninst:
.long NINST
.text
.globl latency
.type latency, @function
.align 32
latency:
push rbp
mov rbp, rsp
xor i, i
test N, N
jle done
# create DP 1.0
vpcmpeqw xmm0, xmm0, xmm0 # all ones
vpsllq xmm0, xmm0, 54 # logical left shift: 11111110..0 (54=64-(10-1))
vpsrlq xmm0, xmm0, 2 # logical right shift: 1 bit for sign; leading mantissa bit is zero
# expand from SSE to AVX
vinsertf128 ymm0, ymm0, xmm0, 0x1
# copy DP 1.0
vmovaps ymm0, ymm0
vmovaps ymm1, ymm0
# Create DP 2.0
vaddpd ymm1, ymm1, ymm1
# Create DP 0.5
vdivpd ymm2, ymm0, ymm1
loop:
inc i
INSTR ymm3, ymm0, ymm0
INSTR ymm4, ymm1, ymm1
INSTR ymm5, ymm2, ymm2
INSTR ymm3, ymm0, ymm0
INSTR ymm4, ymm1, ymm1
INSTR ymm5, ymm2, ymm2
INSTR ymm6, ymm0, ymm0
INSTR ymm7, ymm1, ymm1
INSTR ymm8, ymm2, ymm2
INSTR ymm9, ymm0, ymm0
INSTR ymm10, ymm1, ymm1
INSTR ymm11, ymm2, ymm2
INSTR ymm12, ymm0, ymm0
INSTR ymm13, ymm1, ymm1
INSTR ymm14, ymm2, ymm2
INSTR ymm15, ymm0, ymm0
INSTR ymm16, ymm1, ymm1
INSTR ymm17, ymm2, ymm2
INSTR ymm18, ymm0, ymm0
INSTR ymm19, ymm1, ymm1
INSTR ymm20, ymm2, ymm2
INSTR ymm21, ymm0, ymm0
INSTR ymm22, ymm1, ymm1
INSTR ymm23, ymm2, ymm2
cmp i, N
jl loop
done:
mov rsp, rbp
pop rbp
ret
.size latency, .-latency

View File

@@ -1,67 +0,0 @@
#define INSTR vxorpd
#define NINST 24
#define N edi
#define i r8d
.intel_syntax noprefix
.globl ninst
.data
ninst:
.long NINST
.text
.globl latency
.type latency, @function
.align 32
latency:
push rbp
mov rbp, rsp
xor i, i
test N, N
jle done
# create DP 1.0
vpcmpeqw xmm0, xmm0, xmm0 # all ones
vpsllq xmm0, xmm0, 54 # logical left shift: 11111110..0 (54=64-(10-1))
vpsrlq xmm0, xmm0, 2 # logical right shift: 1 bit for sign; leading mantissa bit is zero
# expand from SSE to AVX
vinsertf128 ymm0, ymm0, xmm0, 0x1
# copy DP 1.0
vmovaps ymm0, ymm0
vmovaps ymm1, ymm0
# Create DP 2.0
vaddpd ymm1, ymm1, ymm1
# Create DP 0.5
vdivpd ymm2, ymm0, ymm1
loop:
inc i
INSTR ymm0, ymm1, ymm0
INSTR ymm1, ymm0, ymm0
INSTR ymm0, ymm1, ymm0
INSTR ymm1, ymm0, ymm0
INSTR ymm0, ymm1, ymm0
INSTR ymm1, ymm0, ymm0
INSTR ymm0, ymm1, ymm0
INSTR ymm1, ymm0, ymm0
INSTR ymm0, ymm1, ymm0
INSTR ymm1, ymm0, ymm0
INSTR ymm0, ymm1, ymm0
INSTR ymm1, ymm0, ymm0
INSTR ymm0, ymm1, ymm0
INSTR ymm1, ymm0, ymm0
INSTR ymm0, ymm1, ymm0
INSTR ymm1, ymm0, ymm0
INSTR ymm0, ymm1, ymm0
INSTR ymm1, ymm0, ymm0
INSTR ymm0, ymm1, ymm0
INSTR ymm1, ymm0, ymm0
INSTR ymm0, ymm1, ymm0
INSTR ymm1, ymm0, ymm0
INSTR ymm0, ymm1, ymm0
INSTR ymm1, ymm0, ymm0
cmp i, N
jl loop
done:
mov rsp, rbp
pop rbp
ret
.size latency, .-latency

View File

@@ -1,65 +0,0 @@
#define INSTR vxorpd
#define NINST 24
#define N edi
#define i r8d
.intel_syntax noprefix
.globl ninst
.data
ninst:
.long NINST
.text
.globl latency
.type latency, @function
.align 32
latency:
push rbp
mov rbp, rsp
xor i, i
test N, N
jle done
# create DP 1.0
vpcmpeqw xmm0, xmm0, xmm0 # all ones
vpsllq xmm0, xmm0, 54 # logical left shift: 11111110..0 (54=64-(10-1))
vpsrlq xmm0, xmm0, 2 # logical right shift: 1 bit for sign; leading mantissa bit is zero
# copy DP 1.0
vmovaps xmm0, xmm0
vmovaps xmm1, xmm0
# Create DP 2.0
vaddpd xmm1, xmm1, xmm1
# Create DP 0.5
vdivpd xmm2, xmm0, xmm1
loop:
inc i
INSTR xmm3, xmm0, xmm0
INSTR xmm4, xmm1, xmm1
INSTR xmm5, xmm2, xmm2
INSTR xmm3, xmm0, xmm0
INSTR xmm4, xmm1, xmm1
INSTR xmm5, xmm2, xmm2
INSTR xmm6, xmm0, xmm0
INSTR xmm7, xmm1, xmm1
INSTR xmm8, xmm2, xmm2
INSTR xmm9, xmm0, xmm0
INSTR xmm10, xmm1, xmm1
INSTR xmm11, xmm2, xmm2
INSTR xmm12, xmm0, xmm0
INSTR xmm13, xmm1, xmm1
INSTR xmm14, xmm2, xmm2
INSTR xmm15, xmm0, xmm0
INSTR xmm16, xmm1, xmm1
INSTR xmm17, xmm2, xmm2
INSTR xmm18, xmm0, xmm0
INSTR xmm19, xmm1, xmm1
INSTR xmm20, xmm2, xmm2
INSTR xmm21, xmm0, xmm0
INSTR xmm22, xmm1, xmm1
INSTR xmm23, xmm2, xmm2
cmp i, N
jl loop
done:
mov rsp, rbp
pop rbp
ret
.size latency, .-latency

View File

@@ -1,65 +0,0 @@
#define INSTR vxorpd
#define NINST 24
#define N edi
#define i r8d
.intel_syntax noprefix
.globl ninst
.data
ninst:
.long NINST
.text
.globl latency
.type latency, @function
.align 32
latency:
push rbp
mov rbp, rsp
xor i, i
test N, N
jle done
# create DP 1.0
vpcmpeqw xmm0, xmm0, xmm0 # all ones
vpsllq xmm0, xmm0, 54 # logical left shift: 11111110..0 (54=64-(10-1))
vpsrlq xmm0, xmm0, 2 # logical right shift: 1 bit for sign; leading mantissa bit is zero
# copy DP 1.0
vmovaps xmm0, xmm0
vmovaps xmm1, xmm0
# Create DP 2.0
vaddpd xmm1, xmm1, xmm1
# Create DP 0.5
vdivpd xmm2, xmm0, xmm1
loop:
inc i
INSTR xmm0, xmm1, xmm0
INSTR xmm1, xmm0, xmm0
INSTR xmm0, xmm1, xmm0
INSTR xmm1, xmm0, xmm0
INSTR xmm0, xmm1, xmm0
INSTR xmm1, xmm0, xmm0
INSTR xmm0, xmm1, xmm0
INSTR xmm1, xmm0, xmm0
INSTR xmm0, xmm1, xmm0
INSTR xmm1, xmm0, xmm0
INSTR xmm0, xmm1, xmm0
INSTR xmm1, xmm0, xmm0
INSTR xmm0, xmm1, xmm0
INSTR xmm1, xmm0, xmm0
INSTR xmm0, xmm1, xmm0
INSTR xmm1, xmm0, xmm0
INSTR xmm0, xmm1, xmm0
INSTR xmm1, xmm0, xmm0
INSTR xmm0, xmm1, xmm0
INSTR xmm1, xmm0, xmm0
INSTR xmm0, xmm1, xmm0
INSTR xmm1, xmm0, xmm0
INSTR xmm0, xmm1, xmm0
INSTR xmm1, xmm0, xmm0
cmp i, N
jl loop
done:
mov rsp, rbp
pop rbp
ret
.size latency, .-latency

View File

@@ -1,65 +0,0 @@
#define INSTR vxorps
#define NINST 24
#define N edi
#define i r8d
.intel_syntax noprefix
.globl ninst
.data
ninst:
.long NINST
.text
.globl latency
.type latency, @function
.align 32
latency:
push rbp
mov rbp, rsp
xor i, i
test N, N
jle done
# create DP 1.0
vpcmpeqw xmm0, xmm0, xmm0 # all ones
vpsllq xmm0, xmm0, 54 # logical left shift: 11111110..0 (54=64-(10-1))
vpsrlq xmm0, xmm0, 2 # logical right shift: 1 bit for sign; leading mantissa bit is zero
# copy DP 1.0
vmovaps xmm0, xmm0
vmovaps xmm1, xmm0
# Create DP 2.0
vaddpd xmm1, xmm1, xmm1
# Create DP 0.5
vdivpd xmm2, xmm0, xmm1
loop:
inc i
INSTR xmm3, xmm0, xmm0
INSTR xmm4, xmm1, xmm1
INSTR xmm5, xmm2, xmm2
INSTR xmm3, xmm0, xmm0
INSTR xmm4, xmm1, xmm1
INSTR xmm5, xmm2, xmm2
INSTR xmm6, xmm0, xmm0
INSTR xmm7, xmm1, xmm1
INSTR xmm8, xmm2, xmm2
INSTR xmm9, xmm0, xmm0
INSTR xmm10, xmm1, xmm1
INSTR xmm11, xmm2, xmm2
INSTR xmm12, xmm0, xmm0
INSTR xmm13, xmm1, xmm1
INSTR xmm14, xmm2, xmm2
INSTR xmm15, xmm0, xmm0
INSTR xmm16, xmm1, xmm1
INSTR xmm17, xmm2, xmm2
INSTR xmm18, xmm0, xmm0
INSTR xmm19, xmm1, xmm1
INSTR xmm20, xmm2, xmm2
INSTR xmm21, xmm0, xmm0
INSTR xmm22, xmm1, xmm1
INSTR xmm23, xmm2, xmm2
cmp i, N
jl loop
done:
mov rsp, rbp
pop rbp
ret
.size latency, .-latency

View File

@@ -1,65 +0,0 @@
#define INSTR vxorps
#define NINST 24
#define N edi
#define i r8d
.intel_syntax noprefix
.globl ninst
.data
ninst:
.long NINST
.text
.globl latency
.type latency, @function
.align 32
latency:
push rbp
mov rbp, rsp
xor i, i
test N, N
jle done
# create DP 1.0
vpcmpeqw xmm0, xmm0, xmm0 # all ones
vpsllq xmm0, xmm0, 54 # logical left shift: 11111110..0 (54=64-(10-1))
vpsrlq xmm0, xmm0, 2 # logical right shift: 1 bit for sign; leading mantissa bit is zero
# copy DP 1.0
vmovaps xmm0, xmm0
vmovaps xmm1, xmm0
# Create DP 2.0
vaddpd xmm1, xmm1, xmm1
# Create DP 0.5
vdivpd xmm2, xmm0, xmm1
loop:
inc i
INSTR xmm0, xmm1, xmm0
INSTR xmm1, xmm0, xmm0
INSTR xmm0, xmm1, xmm0
INSTR xmm1, xmm0, xmm0
INSTR xmm0, xmm1, xmm0
INSTR xmm1, xmm0, xmm0
INSTR xmm0, xmm1, xmm0
INSTR xmm1, xmm0, xmm0
INSTR xmm0, xmm1, xmm0
INSTR xmm1, xmm0, xmm0
INSTR xmm0, xmm1, xmm0
INSTR xmm1, xmm0, xmm0
INSTR xmm0, xmm1, xmm0
INSTR xmm1, xmm0, xmm0
INSTR xmm0, xmm1, xmm0
INSTR xmm1, xmm0, xmm0
INSTR xmm0, xmm1, xmm0
INSTR xmm1, xmm0, xmm0
INSTR xmm0, xmm1, xmm0
INSTR xmm1, xmm0, xmm0
INSTR xmm0, xmm1, xmm0
INSTR xmm1, xmm0, xmm0
INSTR xmm0, xmm1, xmm0
INSTR xmm1, xmm0, xmm0
cmp i, N
jl loop
done:
mov rsp, rbp
pop rbp
ret
.size latency, .-latency

View File

@@ -1,100 +0,0 @@
#define INSTR xor
#define NINST 24
#define N edi
#define i r8d
.intel_syntax noprefix
.globl ninst
.data
ninst:
.long NINST
.text
.globl latency
.type latency, @function
.align 32
latency:
push rbp
mov rbp, rsp
xor i, i
test N, N
jle done
# create DP 1.0
vpcmpeqw xmm0, xmm0, xmm0 # all ones
vpsllq xmm0, xmm0, 54 # logical left shift: 11111110..0 (54=64-(10-1))
vpsrlq xmm0, xmm0, 2 # logical right shift: 1 bit for sign; leading mantissa bit is zero
push rax
push rbx
push rcx
push rdx
push r9
push r10
push r11
push r12
push r13
push r14
push r15
xor rax, rax
xor rbx, rbx
xor rcx, rcx
xor rdx, rdx
xor r9, r9
xor r10, r10
xor r11, r11
xor r12, r12
xor r13, r13
xor r14, r14
xor r15, r15
# copy DP 1.0
vmovq rax, xmm0
vmovq rbx, xmm0
# Create DP 2.0
add rbx, rax
# Create DP 0.5
div rax
movq rcx, rax
vmovq rax, xmm0
loop:
inc i
INSTR dl, al
INSTR r9l, bl
INSTR r10l, cl
INSTR dl, al
INSTR r9l, bl
INSTR r10l, cl
INSTR r11l, al
INSTR r12l, bl
INSTR r13l, cl
INSTR r14l, al
INSTR r15l, bl
INSTR al, cl
INSTR bl, al
INSTR cl, bl
INSTR dl, cl
INSTR r9l, al
INSTR r10l, bl
INSTR r11l, cl
INSTR r12l, al
INSTR r13l, bl
INSTR r14l, cl
INSTR r15l, al
INSTR al, bl
INSTR bl, cl
cmp i, N
jl loop
pop r15
pop r14
pop r13
pop r12
pop r11
pop r10
pop r9
pop rdx
pop rcx
pop rbx
pop rax
done:
mov rsp, rbp
pop rbp
ret
.size latency, .-latency

View File

@@ -1,100 +0,0 @@
#define INSTR xor
#define NINST 24
#define N edi
#define i r8d
.intel_syntax noprefix
.globl ninst
.data
ninst:
.long NINST
.text
.globl latency
.type latency, @function
.align 32
latency:
push rbp
mov rbp, rsp
xor i, i
test N, N
jle done
# create DP 1.0
vpcmpeqw xmm0, xmm0, xmm0 # all ones
vpsllq xmm0, xmm0, 54 # logical left shift: 11111110..0 (54=64-(10-1))
vpsrlq xmm0, xmm0, 2 # logical right shift: 1 bit for sign; leading mantissa bit is zero
push rax
push rbx
push rcx
push rdx
push r9
push r10
push r11
push r12
push r13
push r14
push r15
xor rax, rax
xor rbx, rbx
xor rcx, rcx
xor rdx, rdx
xor r9, r9
xor r10, r10
xor r11, r11
xor r12, r12
xor r13, r13
xor r14, r14
xor r15, r15
# copy DP 1.0
vmovq rax, xmm0
vmovq rbx, xmm0
# Create DP 2.0
add rbx, rax
# Create DP 0.5
div rax
movq rcx, rax
vmovq rax, xmm0
loop:
inc i
INSTR al, bl
INSTR bl, al
INSTR al, bl
INSTR bl, al
INSTR al, bl
INSTR bl, al
INSTR al, bl
INSTR bl, al
INSTR al, bl
INSTR bl, al
INSTR al, bl
INSTR bl, al
INSTR al, bl
INSTR bl, al
INSTR al, bl
INSTR bl, al
INSTR al, bl
INSTR bl, al
INSTR al, bl
INSTR bl, al
INSTR al, bl
INSTR bl, al
INSTR al, bl
INSTR bl, al
cmp i, N
jl loop
pop r15
pop r14
pop r13
pop r12
pop r11
pop r10
pop r9
pop rdx
pop rcx
pop rbx
pop rax
done:
mov rsp, rbp
pop rbp
ret
.size latency, .-latency