mirror of
https://github.com/RRZE-HPC/OSACA.git
synced 2025-12-16 09:00:05 +01:00
style update
This commit is contained in:
Jan Laukemann
@@ -78,7 +78,7 @@ class Osaca(object):
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clk_cyc = line.split()[1]
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clk_cyc_tmp = clk_cyc
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clk_cyc = self.validate_val(clk_cyc, instr, True if (clmn == 'TP') else False,
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cyc_list, reci_list)
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cyc_list, reci_list)
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txt_output = True if (clk_cyc_tmp == clk_cyc) else False
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val = -2
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new = False
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@@ -357,7 +357,8 @@ class Osaca(object):
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# Value is probably correct, so round it to the estimated value
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return cyc_list[i]
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# Check reciprocal only if it is a throughput value
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elif(is_tp and reci_list[i]*1.05 > float(clk_cyc) and reci_list[i]*0.95 < float(clk_cyc)):
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elif(is_tp and reci_list[i]*1.05 > float(clk_cyc)
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and reci_list[i]*0.95 < float(clk_cyc)):
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# Value is probably correct, so round it to the estimated value
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return reci_list[i]
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# No value close to an integer or its reciprocal found, we assume the
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@@ -5,9 +5,9 @@ from subprocess import call
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from math import ceil
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from param import Register, MemAddr, Parameter
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class Testcase(object):
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##------------------Constant variables--------------------------
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# ------------------Constant variables--------------------------
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# Lookup tables for regs
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gprs64 = ['rax', 'rbx', 'rcx', 'rdx', 'r9', 'r10', 'r11', 'r12', 'r13', 'r14', 'r15']
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gprs32 = ['eax', 'ebx', 'ecx', 'edx', 'r9d', 'r10d', 'r11d', 'r12d', 'r13d', 'r14d', 'r15d']
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@@ -18,44 +18,46 @@ class Testcase(object):
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ks = ['k0', 'k1', 'k2', 'k3', 'k4', 'k5', 'k6', 'k7']
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bnds = ['bnd0', 'bnd1', 'bnd2', 'bnd3', 'bnd4', 'bnd5', 'bnd6', 'bnd7']
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xmms = ['xmm0', 'xmm1', 'xmm2', 'xmm3', 'xmm4', 'xmm5', 'xmm6', 'xmm7', 'xmm8', 'xmm9',
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'xmm10', 'xmm11', 'xmm12', 'xmm13', 'xmm14', 'xmm15']
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'xmm10', 'xmm11', 'xmm12', 'xmm13', 'xmm14', 'xmm15']
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ymms = ['ymm0', 'ymm1', 'ymm2', 'ymm3', 'ymm4', 'ymm5', 'ymm6', 'ymm7', 'ymm8', 'ymm9',
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'ymm10', 'ymm11', 'ymm12', 'ymm13', 'ymm14', 'ymm15']
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'ymm10', 'ymm11', 'ymm12', 'ymm13', 'ymm14', 'ymm15']
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zmms = ['zmm0', 'zmm1', 'zmm2', 'zmm3', 'zmm4', 'zmm5', 'zmm6', 'zmm7', 'zmm8', 'zmm9',
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'zmm10', 'zmm11', 'zmm12', 'zmm13', 'zmm14', 'zmm15']
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'zmm10', 'zmm11', 'zmm12', 'zmm13', 'zmm14', 'zmm15']
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# Lookup table for memory
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mems = ['[rip+PI]','[rip+PI]','[rip+PI]','[rip+PI]','[rip+PI]','[rip+PI]','[rip+PI]','[rip+PI]']
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mems = ['[rip+PI]', '[rip+PI]', '[rip+PI]', '[rip+PI]', '[rip+PI]', '[rip+PI]', '[rip+PI]',
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'[rip+PI]']
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# Lookup table for immediates
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imds = ['1', '2', '13', '22', '8', '78', '159', '222', '3', '9', '5', '55', '173', '317',
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imds = ['1', '2', '13', '22', '8', '78', '159', '222', '3', '9', '5', '55', '173', '317',
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'254', '255']
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# TODO Differentiate between AVX512 (with additional xmm16-31) and the rest
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# ...
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# ...
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# end TODO
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ops = {'gpr64':gprs64, 'gpr32':gprs32, 'gpr16':gprs16, 'gpr8':gprs8, 'fpu':fpus, 'mmx':mmxs,
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'k':ks, 'bnd':bnds, 'xmm':xmms, 'ymm':ymms, 'zmm':zmms, 'mem':mems, 'imd':imds}
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ops = {'gpr64': gprs64, 'gpr32': gprs32, 'gpr16': gprs16, 'gpr8': gprs8, 'fpu': fpus,
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'mmx': mmxs, 'k': ks, 'bnd': bnds, 'xmm': xmms, 'ymm': ymms, 'zmm': zmms, 'mem': mems,
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'imd': imds}
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# Create Single Precision 1.0
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sp1 = '\t\t# create SP 1.0\n'
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sp1 += '\t\tvpcmpeqw xmm0, xmm0, xmm0\n'
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sp1 += '\t\tvpslld xmm0, xmm0, 25\t\t\t# logical left shift: 11111110..0 (25=32-(8-1))\n'
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sp1 += ('\t\tvpsrld xmm0, xmm0, 2\t\t\t# logical right shift: 1 bit for sign; leading '
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+ 'mantissa bit is zero\n')
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sp1 += '\t\t# copy SP 1.0\n'
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sp1 = ('\t\t# create SP 1.0\n'
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'\t\tvpcmpeqw xmm0, xmm0, xmm0\n'
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'\t\tvpslld xmm0, xmm0, 25\t\t\t# logical left shift: 11111110..0 (25=32-(8-1))\n'
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'\t\tvpsrld xmm0, xmm0, 2\t\t\t# logical right shift: 1 bit for sign; leading '
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'mantissa bit is zero\n'
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'\t\t# copy SP 1.0\n')
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# Create Double Precision 1.0
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dp1 = '\t\t# create DP 1.0\n'
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dp1 += '\t\tvpcmpeqw xmm0, xmm0, xmm0\t\t# all ones\n'
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dp1 += '\t\tvpsllq xmm0, xmm0, 54\t\t\t# logical left shift: 11111110..0 (54=64-(10-1))\n'
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dp1 += ('\t\tvpsrlq xmm0, xmm0, 2\t\t\t# logical right shift: 1 bit for sign; leading '
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+ 'mantissa bit is zero\n')
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dp1 = ('\t\t# create DP 1.0\n'
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'\t\tvpcmpeqw xmm0, xmm0, xmm0\t\t# all ones\n'
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'\t\tvpsllq xmm0, xmm0, 54\t\t\t# logical left shift: 11111110..0 (54=64-(10-1))\n'
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'\t\tvpsrlq xmm0, xmm0, 2\t\t\t# logical right shift: 1 bit for sign; leading '
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'mantissa bit is zero\n')
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# Create epilogue
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done = ('done:\n'
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'\t\tmov\trsp, rbp\n'
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'\t\tpop\trbp\n'
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'\t\tret\n'
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'.size latency, .-latency')
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##----------------------------------------------------------------
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# ----------------------------------------------------------------
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# Constructor
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def __init__(self, _mnemonic, _param_list, _num_instr='32'):
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@@ -67,7 +69,7 @@ class Testcase(object):
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self.op_a, self.op_b, self.op_c, self.gprPush, self.gprPop, self.zeroGPR, self.copy = self.__define_operands()
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self.num_operands = len(self.param_list)
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# Create asm header
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# Create asm header
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self.def_instr, self.ninstr, self.init, self.expand = self.__define_header()
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# Create latency and throughput loop
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self.loop_lat = self.__define_loop_lat()
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@@ -75,10 +77,9 @@ class Testcase(object):
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# Create extension for testcase name
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sep1 = '_' if (self.num_operands > 1) else ''
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sep2 = '_' if (self.num_operands > 2) else ''
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self.extension = ('-'+(self.op_a if ('gpr' not in self.op_a) else 'r' + self.op_a[3:])
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+ sep1 + (self.op_b if ('gpr' not in self.op_b) else 'r'+self.op_b[3:])
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+ sep2 + (self.op_c if ('gpr' not in self.op_c) else 'r'+self.op_c[3:]))
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self.extension = ('-' + (self.op_a if ('gpr' not in self.op_a) else 'r' + self.op_a[3:])
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+ sep1 + (self.op_b if ('gpr' not in self.op_b) else 'r' + self.op_b[3:])
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+ sep2 + (self.op_c if ('gpr' not in self.op_c) else 'r' + self.op_c[3:]))
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def write_testcase(self, TP=True, LT=True):
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"""
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@@ -98,20 +99,19 @@ class Testcase(object):
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# Write latency file
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call(['mkdir', '-p', os.path.dirname(__file__)+'/../testcases'])
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f = open(os.path.dirname(__file__)+'/../testcases/'+self.instr+self.extension+'.S', 'w')
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data = (self.def_instr+self.ninstr+self.init+self.dp1+self.expand+self.gprPush
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+self.zeroGPR+self.copy+self.loop_lat+self.gprPop+self.done)
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data = (self.def_instr + self.ninstr + self.init + self.dp1 + self.expand + self.gprPush
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+ self.zeroGPR + self.copy + self.loop_lat + self.gprPop + self.done)
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f.write(data)
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f.close()
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if(TP):
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# Write throughput file
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f = open(os.path.dirname(__file__)+'/../testcases/'+self.instr+self.extension
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+'-TP.S', 'w')
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data = (self.def_instr+self.ninstr+self.init+self.dp1+self.expand+self.gprPush
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+self.zeroGPR+self.copy+self.loop_thrpt+self.gprPop+self.done)
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f = open(os.path.dirname(__file__) + '/../testcases/' + self.instr + self.extension
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+ '-TP.S', 'w')
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data = (self.def_instr + self.ninstr + self.init + self.dp1 + self.expand + self.gprPush
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+ self.zeroGPR + self.copy + self.loop_thrpt + self.gprPop + self.done)
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f.write(data)
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f.close()
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# Check operands
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def __define_operands(self):
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"""
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@@ -120,7 +120,7 @@ class Testcase(object):
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Returns
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-------
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(str, str, str, str, str, str)
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String tuple containing types of operands and if needed push/pop operations, the
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String tuple containing types of operands and if needed push/pop operations, the
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initialisation of general purpose regs and the copy if registers.
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"""
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oprnds = self.param_list
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@@ -139,7 +139,7 @@ class Testcase(object):
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if(isinstance(oprnds[1], Register)):
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op_b = oprnds[1].reg_type.lower()
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elif(isinstance(oprnds[1], MemAddr)):
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op_b = 'mem'
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op_b = 'mem'
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elif(isinstance(oprnds[1], Parameter) and str(oprnds[1]) == 'IMD'):
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op_b = 'imd'
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if(op_b == 'gpr'):
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@@ -165,8 +165,7 @@ class Testcase(object):
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copy = self.__copy_regs(oprnds[1])
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else:
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copy = ''
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return (op_a, op_b, op_c, gprPush, gprPop, zeroGPR, copy)
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return (op_a, op_b, op_c, gprPush, gprPop, zeroGPR, copy)
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def __initialise_gprs(self):
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"""
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@@ -184,7 +183,7 @@ class Testcase(object):
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for reg in self.gprs64:
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gprPush += '\t\tpush {}\n'.format(reg)
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for reg in reversed(self.gprs64):
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gprPop += '\t\tpop {}\n'.format(reg)
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gprPop += '\t\tpop {}\n'.format(reg)
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for reg in self.gprs64:
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zeroGPR += '\t\txor {}, {}\n'.format(reg, reg)
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return (gprPush, gprPop, zeroGPR)
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@@ -199,7 +198,7 @@ class Testcase(object):
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----------
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reg : Register
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Register for copying the value
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Returns
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-------
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str
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@@ -208,16 +207,16 @@ class Testcase(object):
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copy = '\t\t# copy DP 1.0\n'
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# Different handling for GPR, MMX and SSE/AVX registers
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if(reg.reg_type == 'GPR'):
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copy += '\t\tvmovq {}, xmm0\n'.format(self.ops['gpr64'][0])
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copy += '\t\tvmovq {}, xmm0\n'.format(self.ops['gpr64'][0])
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copy += '\t\tvmovq {}, xmm0\n'.format(self.ops['gpr64'][1])
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copy += '\t\t# Create DP 2.0\n'
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copy += '\t\tadd {}, {}\n'.format(self.ops['gpr64'][1], self.ops['gpr64'][0])
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copy += '\t\t# Create DP 0.5\n'
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copy += '\t\tdiv {}\n'.format(self.ops['gpr64'][0])
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copy += '\t\tmovq {}, {}\n'.format(self.ops['gpr64'][2], self.ops['gpr64'][0])
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copy += '\t\tvmovq {}, xmm0\n'.format(self.ops['gpr64'][0])
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copy += '\t\tvmovq {}, xmm0\n'.format(self.ops['gpr64'][0])
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elif(reg.reg_type == 'MMX'):
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copy += '\t\tvmovq {}, xmm0\n'.format(self.ops['mmx'][0])
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copy += '\t\tvmovq {}, xmm0\n'.format(self.ops['mmx'][0])
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copy += '\t\tvmovq {}, xmm0\n'.format(self.ops['mmx'][1])
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copy += '\t\tvmovq {}, xmm0\n'.format(self.ops['gpr64'][0])
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copy += '\t\t# Create DP 2.0\n'
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@@ -227,19 +226,18 @@ class Testcase(object):
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copy += '\t\tmovq {}, {}\n'.format(self.ops['mmx'][2], self.ops['gpr64'][0])
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elif(reg.reg_type == 'XMM' or reg.reg_type == 'YMM' or reg.reg_type == 'ZMM'):
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key = reg.reg_type.lower()
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copy += '\t\tvmovaps {}, {}\n'.format(self.ops[key][0], self.ops[key][0])
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copy += '\t\tvmovaps {}, {}\n'.format(self.ops[key][0], self.ops[key][0])
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copy += '\t\tvmovaps {}, {}\n'.format(self.ops[key][1], self.ops[key][0])
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copy += '\t\t# Create DP 2.0\n'
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copy += '\t\tvaddpd {}, {}, {}\n'.format(self.ops[key][1], self.ops[key][1],
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self.ops[key][1])
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copy += '\t\tvaddpd {}, {}, {}\n'.format(self.ops[key][1], self.ops[key][1],
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self.ops[key][1])
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copy += '\t\t# Create DP 0.5\n'
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copy += '\t\tvdivpd {}, {}, {}\n'.format(self.ops[key][2], self.ops[key][0],
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self.ops[key][1])
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copy += '\t\tvdivpd {}, {}, {}\n'.format(self.ops[key][2], self.ops[key][0],
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self.ops[key][1])
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else:
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copy = ''
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return copy
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def __define_header(self):
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"""
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Define header.
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@@ -252,30 +250,30 @@ class Testcase(object):
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def_instr = '#define INSTR '+self.instr+'\n'
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ninstr = '#define NINST '+self.num_instr+'\n'
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pi = ('PI:\n'
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'.long 0xf01b866e, 0x400921f9, 0xf01b866e, 0x400921f9, ' #128 bit
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'0xf01b866e, 0x400921f9, 0xf01b866e, 0x400921f9, ' #256 bit
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'0xf01b866e, 0x400921f9, 0xf01b866e, 0x400921f9, ' #384 bit
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'0xf01b866e, 0x400921f9, 0xf01b866e, 0x400921f9\n') #512 bit
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init = ('#define N edi\n' \
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'#define i r8d\n\n\n'
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'.intel_syntax noprefix\n'
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'.globl ninst\n'
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'.data\n'
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'ninst:\n'
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'.long NINST\n'
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'.align 32\n'
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+pi+
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'.text\n'
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'.globl latency\n'
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'.type latency, @function\n'
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'.align 32\n'
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'latency:\n'
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'\t\tpush rbp\n'
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'\t\tmov rbp, rsp\n'
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'\t\txor i, i\n'
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'\t\ttest N, N\n'
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'\t\tjle done\n')
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# Expand to AVX(512) if necessary
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'.long 0xf01b866e, 0x400921f9, 0xf01b866e, 0x400921f9, ' # 128 bit
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'0xf01b866e, 0x400921f9, 0xf01b866e, 0x400921f9, ' # 256 bit
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'0xf01b866e, 0x400921f9, 0xf01b866e, 0x400921f9, ' # 384 bit
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'0xf01b866e, 0x400921f9, 0xf01b866e, 0x400921f9\n') # 512 bit
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init = ('#define N edi\n'
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'#define i r8d\n\n\n'
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'.intel_syntax noprefix\n'
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'.globl ninst\n'
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'.data\n'
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'ninst:\n'
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'.long NINST\n'
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'.align 32\n'
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+ pi +
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'.text\n'
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'.globl latency\n'
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'.type latency, @function\n'
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'.align 32\n'
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'latency:\n'
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'\t\tpush rbp\n'
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'\t\tmov rbp, rsp\n'
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'\t\txor i, i\n'
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'\t\ttest N, N\n'
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'\t\tjle done\n')
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# Expand to AVX(512) if necessary
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expand = ''
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if(self.op_a == 'ymm' or self.op_b == 'ymm' or self.op_c == 'ymm'):
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expand = ('\t\t# expand from SSE to AVX\n'
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@@ -287,7 +285,6 @@ class Testcase(object):
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'\t\tvinsert64x4 zmm0, zmm0, ymm0, 0x1\n')
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return (def_instr, ninstr, init, expand)
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def __define_loop_lat(self):
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"""
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Create latency loop.
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@@ -304,33 +301,36 @@ class Testcase(object):
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loop_lat += '\t\tINSTR {}\n'.format(self.ops[self.op_a][0])
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elif(self.num_operands == 2 and self.op_a == self.op_b):
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for i in range(0, int(self.num_instr), 2):
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loop_lat += '\t\tINSTR {}, {}\n'.format(self.ops[self.op_a][0],
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loop_lat += '\t\tINSTR {}, {}\n'.format(self.ops[self.op_a][0],
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self.ops[self.op_b][1])
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loop_lat += '\t\tINSTR {}, {}\n'.format(self.ops[self.op_b][1],
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loop_lat += '\t\tINSTR {}, {}\n'.format(self.ops[self.op_b][1],
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self.ops[self.op_b][0])
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elif(self.num_operands == 2 and self.op_a != self.op_b):
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for i in range(0, int(self.num_instr), 2):
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loop_lat += '\t\tINSTR {}, {}\n'.format(self.ops[self.op_a][0],
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loop_lat += '\t\tINSTR {}, {}\n'.format(self.ops[self.op_a][0],
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self.ops[self.op_b][0])
|
||||
loop_lat += '\t\tINSTR {}, {}\n'.format(self.ops[self.op_a][0],
|
||||
loop_lat += '\t\tINSTR {}, {}\n'.format(self.ops[self.op_a][0],
|
||||
self.ops[self.op_b][0])
|
||||
elif(self.num_operands == 3 and self.op_a == self.op_b):
|
||||
for i in range(0, int(self.num_instr), 2):
|
||||
loop_lat += '\t\tINSTR {}, {}, {}\n'.format(self.ops[self.op_a][0],
|
||||
self.ops[self.op_b][1], self.ops[self.op_c][0])
|
||||
loop_lat += '\t\tINSTR {}, {}, {}\n'.format(self.ops[self.op_a][1],
|
||||
self.ops[self.op_b][0], self.ops[self.op_c][0])
|
||||
loop_lat += '\t\tINSTR {}, {}, {}\n'.format(self.ops[self.op_a][0],
|
||||
self.ops[self.op_b][1],
|
||||
self.ops[self.op_c][0])
|
||||
loop_lat += '\t\tINSTR {}, {}, {}\n'.format(self.ops[self.op_a][1],
|
||||
self.ops[self.op_b][0],
|
||||
self.ops[self.op_c][0])
|
||||
elif(self.num_operands == 3 and self.op_a == self.op_c):
|
||||
for i in range(0, int(self.num_instr), 2):
|
||||
loop_lat += '\t\tINSTR {}, {}, {}\n'.format(self.ops[self.op_a][0],
|
||||
self.ops[self.op_b][0], self.ops[self.op_c][0])
|
||||
loop_lat += '\t\tINSTR {}, {}, {}\n'.format(self.ops[self.op_a][1],
|
||||
self.ops[self.op_b][0], self.ops[self.op_c][0])
|
||||
loop_lat += '\t\tINSTR {}, {}, {}\n'.format(self.ops[self.op_a][0],
|
||||
self.ops[self.op_b][0],
|
||||
self.ops[self.op_c][0])
|
||||
loop_lat += '\t\tINSTR {}, {}, {}\n'.format(self.ops[self.op_a][1],
|
||||
self.ops[self.op_b][0],
|
||||
self.ops[self.op_c][0])
|
||||
loop_lat += ('\t\tcmp i, N\n'
|
||||
'\t\tjl loop\n')
|
||||
return loop_lat
|
||||
|
||||
|
||||
def __define_loop_thrpt(self):
|
||||
"""
|
||||
Create throughput loop.
|
||||
@@ -352,16 +352,15 @@ class Testcase(object):
|
||||
ext2 = True
|
||||
for i in range(0, int(self.num_instr)):
|
||||
if(ext1):
|
||||
ext = ', {}'.format(self.ops[self.op_b][i%3])
|
||||
ext = ', {}'.format(self.ops[self.op_b][i % 3])
|
||||
if(ext2):
|
||||
ext += ', {}'.format(self.ops[self.op_c][i%3])
|
||||
regNum = (i%(len(self.ops[self.op_a])-3))+3
|
||||
ext += ', {}'.format(self.ops[self.op_c][i % 3])
|
||||
regNum = (i % (len(self.ops[self.op_a]) - 3)) + 3
|
||||
loop_thrpt += '\t\tINSTR {}{}\n'.format(self.ops[self.op_a][regNum], ext)
|
||||
loop_thrpt += ('\t\tcmp i, N\n'
|
||||
'\t\tjl loop\n')
|
||||
'\t\tjl loop\n')
|
||||
return loop_thrpt
|
||||
|
||||
|
||||
def is_in_dir(self):
|
||||
"""
|
||||
Check if testcases with the same name already exist in testcase
|
||||
@@ -383,4 +382,4 @@ class Testcase(object):
|
||||
TP = True
|
||||
if name+'.S' in files:
|
||||
LT = True
|
||||
return (TP,LT)
|
||||
return (TP, LT)
|
||||
|
||||
Reference in New Issue
Block a user