mirror of
https://github.com/RRZE-HPC/OSACA.git
synced 2026-01-05 10:40:06 +01:00
ibench benchmark file creation
This commit is contained in:
JanLJL
@@ -1,41 +1,265 @@
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#!/usr/bin/env python3
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import copy
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import os
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from jinja2 import Template
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from osaca.parser import ParserAArch64v81, ParserX86ATT
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BENCHMARK_DIR = os.path.expanduser('~/.osaca/benchmarks')
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class IbenchAPI(object):
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def __init__(self, isa):
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# TODO
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self.isa = isa.lower()
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self.ibench_dir = os.path.join(BENCHMARK_DIR, 'ibench', self.isa)
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if not os.path.isdir(self.ibench_dir):
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os.makedirs(self.ibench_dir)
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def create_ubenchmark(self):
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# TODO
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def create_ubenchmark(self, instruction_form):
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if self.isa == 'aarch64':
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self.create_ubench_aarch64()
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self.parser = ParserAArch64v81()
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tp_bench, lt_bench = self._create_ubench_aarch(instruction_form)
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elif self.isa == 'x86':
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self.create_ubench_x86()
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self.parser = ParserX86ATT()
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tp_bench, lt_bench = self._create_ubench_x86(instruction_form)
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if tp_bench is None or lt_bench is None:
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return
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self._write_benchmark(self._get_ibench_name(instruction_form) + '-TP.S', tp_bench)
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self._write_benchmark(self._get_ibench_name(instruction_form) + '-LT.S', lt_bench)
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def import_ibench_output(self, filepath):
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# TODO
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assert os.path.exists(filepath)
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raise NotImplementedError
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def create_ubench_aarch(self):
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# TODO
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raise NotImplementedError
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##########################################
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##########################################
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def create_ubench_x86(self):
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# TODO
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raise NotImplementedError
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def _write_benchmark(self, filename, content):
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with open(os.path.join(self.ibench_dir, filename), 'w') as f:
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f.write(content)
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def _get_ibench_name(self, instruction_form):
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name = ''
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op_sep = '_'
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name += instruction_form['instruction'].lower() + '-'
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operands = (
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instruction_form['operands']['operand_list']
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if 'operand_list' in instruction_form['operands']
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else instruction_form['operands']
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)
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if self.isa == 'aarch64':
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for op in operands:
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if 'register' in op:
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name += op['register']['prefix']
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name += op['register']['shape'] if 'shape' in op['register'] else ''
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elif 'immediate' in op:
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name += 'i'
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else:
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raise NotImplementedError
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name += op_sep
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elif self.isa == 'x86':
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for op in operands:
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if 'register' in op:
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name += (
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'r' if self.parser.is_gpr(op['register']) else op['register']['name'][0]
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)
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elif 'immediate' in op:
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name += 'i'
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name += op_sep
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else:
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raise NotImplementedError(
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'Currently only AArch64 and x86 architectures are supported.'
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)
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return name[:-1]
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def _create_ubench_aarch(self, instruction_form, num_instructions=8):
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loop_kernel_tp = ''
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loop_kernel_lt = ''
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vector_regs = False
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gp_regs = False
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mnemonic = instruction_form['instruction']
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operands = (
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instruction_form['operands']['operand_list']
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if 'operand_list' in instruction_form['operands']
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else instruction_form['operands']
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)
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for op in operands:
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if 'register' in op:
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if self.parser.is_gpr(op['register']):
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gp_regs = True
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elif self.parser.is_vector_register(op['register']):
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vector_regs = True
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elif 'memory' in op:
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return None, None
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num_regs = len([x for x in operands if 'register' in x])
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# throughput benchmark
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possible_regs_tp = list(range(5, 16)) + list(range(19, 29))
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i = 0
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while i < num_instructions * num_regs:
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ops = []
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for op in operands:
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name = possible_regs_tp[i % len(possible_regs_tp)]
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ops.append(self._get_aarch_op(op, name))
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i += 1 if 'register' in op else 0
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line = '\tINSTR {}\n'.format(', '.join(ops))
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loop_kernel_tp += line
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# latency benchmark
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possible_regs_lt = list(range(5, 5 + num_regs))
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operands_lt = copy.deepcopy(operands)
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for i, x in enumerate(operands_lt):
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operands_lt[i] = (
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self._get_aarch_op(x, possible_regs_lt.pop())
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if 'register' in x
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else self._get_aarch_op(x, 0)
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)
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for i in range(0, 6):
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line = '\tINSTR {}\n'.format(', '.join(operands_lt))
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loop_kernel_lt += line
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operands_lt = self._invert_regs(operands, operands_lt)
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args_tp = {
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'instr': mnemonic,
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'ninst': num_instructions,
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'vector_regs': vector_regs,
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'gp_regs': gp_regs,
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'loop_kernel': loop_kernel_tp,
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}
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args_lt = {
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'instr': mnemonic,
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'ninst': 6,
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'vector_regs': vector_regs,
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'gp_regs': gp_regs,
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'loop_kernel': loop_kernel_lt,
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}
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return template_aarch64.render(**args_tp), template_aarch64.render(**args_lt)
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def _create_ubench_x86(self, instruction_form, num_instructions=8):
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loop_kernel_tp = ''
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loop_kernel_lt = ''
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gp_regs = False
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AVX = False
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AVX512 = False
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mnemonic = instruction_form['instruction']
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operands = list(
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reversed(
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copy.deepcopy(
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instruction_form['operands']['operand_list']
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if 'operand_list' in instruction_form['operands']
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else instruction_form['operands']
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)
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)
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)
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for op in operands:
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if 'register' in op:
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if self.parser.is_gpr(op['register']):
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gp_regs = True
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elif op['register']['name'][0].lower() == 'y':
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AVX = True
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elif op['register']['name'][0].lower() == 'z':
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AVX512 = True
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elif 'memory' in op:
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return None, None
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num_regs = len([x for x in operands if 'register' in x])
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# throughput benchmark
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possible_regs_tp = {
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'gpr': ['ax', 'bx', 'cx', 'dx'] + list(range(9, 16)),
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'vector': list(range(0, 16)),
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}
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gpr_i = 0
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vector_i = 0
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for i in range(num_instructions):
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ops = []
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for op in operands:
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name = 0
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if 'register' in op:
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if self.parser.is_gpr(op['register']):
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name = possible_regs_tp['gpr'][gpr_i % len(possible_regs_tp['gpr'])]
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gpr_i += 1
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else:
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name = possible_regs_tp['vector'][
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vector_i % len(possible_regs_tp['vector'])
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]
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vector_i += 1
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ops.append(self._get_x86_op(op, name))
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line = '\tINSTR {}\n'.format(', '.join(ops))
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loop_kernel_tp += line
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# latency benchmark
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possible_regs_lt = list(range(9, 9 + num_regs))
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operands_lt = copy.deepcopy(operands)
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for i, x in enumerate(operands_lt):
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operands_lt[i] = (
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self._get_x86_op(x, possible_regs_lt.pop())
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if 'register' in x
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else self._get_x86_op(x, 0)
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)
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for i in range(0, 6):
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line = '\tINSTR {}\n'.format(', '.join(operands_lt))
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loop_kernel_lt += line
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operands_lt = self._invert_regs(operands, operands_lt)
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args_tp = {
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'instr': mnemonic,
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'ninst': num_instructions,
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'gp_regs': gp_regs,
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'AVX': AVX,
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'AVX512': AVX512,
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'loop_kernel': loop_kernel_tp.rstrip(),
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}
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args_lt = {
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'instr': mnemonic,
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'ninst': num_instructions,
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'gp_regs': gp_regs,
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'AVX': AVX,
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'AVX512': AVX512,
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'loop_kernel': loop_kernel_lt.rstrip(),
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}
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return template_x86.render(**args_tp), template_x86.render(**args_lt)
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def _get_aarch_op(self, operand, name):
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operand = copy.deepcopy(operand)
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if 'register' in operand:
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operand['register']['name'] = name
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return self.parser.get_full_reg_name(operand['register'])
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elif 'immediate' in operand:
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return '#192'
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else:
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raise NotImplementedError('Only immediates and register in benchmark allowed')
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def _get_x86_op(self, operand, name):
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operand = copy.deepcopy(operand)
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if 'register' in operand:
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reg_type = self.parser.get_reg_type(operand['register'])
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reg_type = reg_type[-1] if reg_type.startswith('gp') else reg_type
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operand['register']['name'] = reg_type + str(name)
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return self.parser.get_full_reg_name(operand['register'])
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elif 'immediate' in operand:
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return '192'
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else:
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raise NotImplementedError('Only immediates and register in benchmark allowed')
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def _invert_regs(self, operands, operand_str_list):
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reg_indices = [i for i, op in enumerate(operands) if 'register' in op]
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reg_indices_inverted = list(reversed(reg_indices))
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operands_tmp = [None for x in operand_str_list]
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for i in range(len(operand_str_list)):
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operands_tmp[i] = (
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operand_str_list[reg_indices_inverted[i]]
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if i in reg_indices
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else operand_str_list[i]
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)
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return operands_tmp
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# TODO
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# template_x86 = Template()
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template_aarch64 = Template(
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'''
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#define INSTR {{ instr }}
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'''#define INSTR {{ instr }}
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#define NINST {{ ninst }}
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#define N x0
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@@ -43,16 +267,11 @@ template_aarch64 = Template(
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.data
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ninst:
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.long NINST
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{% if imd %}
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IMD:
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.long 0xf01b866e, 0x400921f9, 0xf01b866e, 0x400921f9
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{% endif %}
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.text
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.globl latency
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.type latency, @function
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.globl benchmark
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.type benchmark, @function
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.align 32
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latency:
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benchmark:
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{% if vector_regs %}
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# push callee-save registers onto stack
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sub sp, sp, #64
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@@ -60,29 +279,31 @@ latency:
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sub sp, sp, #64
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st1 {v12.4s, v13.4s, v14.4s, v15.4s}, [sp]
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mov x4, N
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fmov v0.2d, #1.00000000
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fmov v1.2d, #1.00000000
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fmov v2.2d, #1.00000000
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fmov v3.2d, #1.00000000
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fmov v4.2d, #1.00000000
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fmov v5.2d, #1.00000000
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fmov v6.2d, #1.00000000
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fmov v7.2d, #1.00000000
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fmov v8.2d, #1.00000000
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fmov v9.2d, #1.00000000
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fmov v10.2d, #1.00000000
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fmov v11.2d, #1.00000000
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fmov v12.2d, #1.00000000
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fmov v13.2d, #1.00000000
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fmov v14.2d, #1.00000000
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fmov v15.2d, #1.00000000
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fmov v0.2d, #1.20000000
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fmov v1.2d, #1.23000000
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fmov v2.2d, #1.23400000
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fmov v3.2d, #1.23410000
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fmov v4.2d, #1.23412000
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fmov v5.2d, #1.23412300
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fmov v6.2d, #1.23412340
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fmov v7.2d, #1.23412341
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fmov v8.2d, #2.34123412
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fmov v9.2d, #2.34123410
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fmov v10.2d, #2.34123400
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fmov v11.2d, #2.34123000
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fmov v12.2d, #2.34120000
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fmov v13.2d, #2.34100000
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fmov v14.2d, #2.34000000
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fmov v15.2d, #2.30000000
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{% endif %}
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{% if gp_regs %}
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# push callee-save register onto stack
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push {x19-x28}
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{% endif %}
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loop:
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{{ loop_kernel }}
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subs x4, x4, #1
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{{ loop_kernel }}
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bne loop
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done:
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@@ -94,9 +315,112 @@ done:
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add sp, sp, #64
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{% endif %}
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{% if gp_regs %}
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pop {x19-x28}
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{% endif %}
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ret
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.size latency, .-latency
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.size benchmark, .-benchmark
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'''
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)
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template_x86 = Template(
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'''#define INSTR {{ instr }}
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#define NINST {{ ninst }}
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#define N edi
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#define i r8d
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.intel_syntax noprefix
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.globl ninst
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.data
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ninst:
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.long NINST
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.text
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.globl benchmark
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.type benchmark, @function
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.align 32
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benchmark:
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push rbp
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mov rbp, rsp
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xor i, i
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test N, N
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jle done
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{% if gp_regs %}
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push rax
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push rbx
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push rcx
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push rdx
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push r9
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push r10
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push r11
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push r12
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push r13
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push r14
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push r15
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mov rax, 1
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mov rbx, 2
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mov rcx, 3
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mov rdx, 4
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mov r9, 5
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mov r10, 6
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mov r11, 7
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mov r12, 8
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mov r13, 9
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mov r14, 10
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mov r15, 11
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{% endif %}
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# create SP 1.0
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vpcmpeqw xmm0, xmm0, xmm0 # all ones
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vpslld xmm0, xmm0, 25 # logical left shift: 11111110..0 (25 = 32 - (8 - 1))
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vpsrld xmm0, xmm0, 2 # logical right shift: 1 bit for sign; leading mantissa bit is 0
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{% if AVX or AVX512 %}
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# expand from SSE to AVX
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vinsertf128 ymm0, ymm0, xmm0, 0x1
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{% endif %}
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{% if AVX512 %}
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# expand from AVX to AVX-512
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vinsertf64x4 zmm0, zmm0, ymm0, 0x1
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{% endif %}
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{% if not AVX and not AVX512 %}
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# create SP 2.0
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vaddps xmm1, xmm0, xmm0
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# create SP 0.5
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vdivps xmm2, xmm0, xmm1
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{% endif %}
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{% if AVX and not AVX512 %}
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# create SP 2.0
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vaddps ymm1, ymm0, ymm0
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# create SP 0.5
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vdivps ymm2, ymm0, ymm1
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{% endif %}
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{% if AVX512 %}
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# create AVX-512 DP 2.0
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vaddps zmm1, zmm0, zmm0
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# create AVX-512 DP 0.5
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vdivps zmm2, zmm0, zmm1
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{% endif %}
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loop:
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inc i
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{{ loop_kernel }}
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cmp i, N
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jl loop
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done:
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{% if gp_regs %}
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pop r15
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pop r14
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pop r13
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pop r12
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pop r11
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pop r10
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pop r9
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pop rdx
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pop rcx
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pop rbx
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pop rax
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{% endif %}
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mov rsp, rbp
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pop rbp
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ret
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.size benchmark, .-benchmark
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'''
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)
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@@ -151,6 +151,15 @@ instruction_forms:
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throughput: 0.5
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latency: 4.0 # 0 0DV 1 2 2D 3 3D 4 5 6 7
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port_pressure: [0.5, 0.0, 0.5, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0]
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- name: movl
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operands:
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- class: "register"
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name: "gpr"
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- class: "register"
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name: "gpr"
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throughput: 0.0
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latency: 1.0 # 0 0DV 1 2 2D 3 3D 4 5 6 7
|
||||
port_pressure: [0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0]
|
||||
- name: rcpss
|
||||
operands:
|
||||
- class: "register"
|
||||
@@ -361,6 +370,18 @@ instruction_forms:
|
||||
throughput: 0.0
|
||||
latency: 0.0 # 0 0DV 1 2 2D 3 3D 4 5 6 7
|
||||
port_pressure: [0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0]
|
||||
- name: vmovapd
|
||||
operands:
|
||||
- class: "memory"
|
||||
base: "gpr"
|
||||
offset: "imd"
|
||||
index: "gpr"
|
||||
scale: 1
|
||||
- class: "register"
|
||||
name: "ymm"
|
||||
throughput: 1.0
|
||||
latency: 4.0 # 0 0DV 1 2 2D 3 3D 4 5 6 7
|
||||
port_pressure: [0.0, 0.0, 0.0, 0.5, 0.5, 0.5, 0.5, 0.0, 0.0, 0.0, 0.0]
|
||||
- name: vmovapd
|
||||
operands:
|
||||
- class: "register"
|
||||
|
||||
@@ -5,6 +5,16 @@ isa: "x86"
|
||||
# mnemonic op1 ... opN
|
||||
# means that opN is the only destination operand and op1 to op(N-1) are source operands.
|
||||
instruction_forms:
|
||||
- name: addl
|
||||
operands:
|
||||
- class: "immediate"
|
||||
imd: "int"
|
||||
source: true
|
||||
destination: false
|
||||
- class: "register"
|
||||
name: "gpr"
|
||||
source: true
|
||||
destination: true
|
||||
- name: addq
|
||||
operands:
|
||||
- class: "immediate"
|
||||
|
||||
Reference in New Issue
Block a user