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bugfixes

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This commit is contained in:
JanLJL
2020-11-21 21:00:58 +01:00
parent 08b4586b71
commit 596a323dfb
2 changed files with 9 additions and 8 deletions
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9
osaca/parser/parser_x86att.py
View File

@@ -406,7 +406,10 @@ class ParserX86ATT(BaseParser):
def is_basic_gpr(self, register): def is_basic_gpr(self, register):
"""Check if register is a basic general purpose register (ebi, rax, ...)""" """Check if register is a basic general purpose register (ebi, rax, ...)"""
if any(char.isdigit() for char in register['name']): if (
any(char.isdigit() for char in register['name'])
or any(register['name'].lower().startswith(x) for x in ['mm', 'xmm', 'ymm', 'zmm'])
):
return False return False
return True return True
@@ -414,10 +417,8 @@ class ParserX86ATT(BaseParser):
"""Check if register is a general purpose register""" """Check if register is a general purpose register"""
if register is None: if register is None:
return False return False
if self.is_basic_gpr(register): if self.is_basic_gpr(register):
return True return True
return re.match(r'R([0-9]+)[DWB]?', register['name'], re.IGNORECASE) return re.match(r'R([0-9]+)[DWB]?', register['name'], re.IGNORECASE)
def is_vector_register(self, register): def is_vector_register(self, register):
@@ -429,7 +430,7 @@ class ParserX86ATT(BaseParser):
return False return False
def get_reg_type(self, register): def get_reg_type(self, register):
"""Ger register type""" """Get register type"""
if register is None: if register is None:
return False return False
if self.is_gpr(register): if self.is_gpr(register):

8
osaca/semantics/hw_model.py
View File

@@ -187,8 +187,8 @@ class MachineModel(object):
"""Return load thorughput for given register type.""" """Return load thorughput for given register type."""
ld_tp = [m for m in self._data['load_throughput'] if self._match_mem_entries(memory, m)] ld_tp = [m for m in self._data['load_throughput'] if self._match_mem_entries(memory, m)]
if len(ld_tp) > 0: if len(ld_tp) > 0:
return ld_tp[0]['port_pressure'] return ld_tp[0]['port_pressure'].copy()
return self._data['load_throughput_default'] return self._data['load_throughput_default'].copy()
def get_store_latency(self, reg_type): def get_store_latency(self, reg_type):
"""Return store latency for given register type.""" """Return store latency for given register type."""
@@ -199,8 +199,8 @@ class MachineModel(object):
"""Return store throughput for given register type.""" """Return store throughput for given register type."""
st_tp = [m for m in self._data['store_throughput'] if self._match_mem_entries(memory, m)] st_tp = [m for m in self._data['store_throughput'] if self._match_mem_entries(memory, m)]
if len(st_tp) > 0: if len(st_tp) > 0:
return st_tp[0]['port_pressure'] return st_tp[0]['port_pressure'].copy()
return self._data['store_throughput_default'] return self._data['store_throughput_default'].copy()
def _match_mem_entries(self, mem, i_mem): def _match_mem_entries(self, mem, i_mem):
"""Check if memory addressing ``mem`` and ``i_mem`` are of the same type.""" """Check if memory addressing ``mem`` and ``i_mem`` are of the same type."""