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simple implement for TSV110

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Qingcai Jiang
2021-11-06 16:04:16 +08:00
parent c97f93c39b
commit 7194e79beb
3 changed files with 91 additions and 1 deletions
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88
osaca/data/tsv110.yml Normal file
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@@ -0,0 +1,88 @@
osaca_version: 0.4.6
micro_architecture: TaiShan v110
arch_code: tsv110
isa: AArch64
ROB_size: 128
retired_uOps_per_cycle: 4
scheduler_size: "*"
hidden_loads: false
load_latency: {w: 4.0, x: 4.0, b: 4.0, h: 4.0, s: 4.0, d: 4.0, q: 4.0, v: 4.0}
load_throughput:
- {base: x, index: ~, offset: ~, scale: 1, pre-indexed: false, post-indexed: false, port_pressure: [[1, '34'], [1, '012']]}
- {base: x, index: ~, offset: imd, scale: 1, pre-indexed: false, post-indexed: true, port_pressure: [[1, '34'], [1, '012']]}
- {base: x, index: ~, offset: imd, scale: 1, pre-indexed: false, post-indexed: false, port_pressure: [[1, '34'], [1, '012']]}
- {base: x, index: ~, offset: imd, scale: 1, pre-indexed: true, post-indexed: true, port_pressure: [[1, '34'], [1, '012']]}
- {base: x, index: ~, offset: imd, scale: 1, pre-indexed: true, post-indexed: false, port_pressure: [[1, '34'], [1, '012']]}
- {base: x, index: x, offset: ~, scale: 1, pre-indexed: false, post-indexed: true, port_pressure: [[1, '34'], [1, '012']]}
- {base: x, index: x, offset: ~, scale: 1, pre-indexed: false, post-indexed: false, port_pressure: [[1, '34'], [1, '012']]}
- {base: x, index: x, offset: ~, scale: 1, pre-indexed: true, post-indexed: true, port_pressure: [[1, '34'], [1, '012']]}
- {base: x, index: x, offset: ~, scale: 1, pre-indexed: true, post-indexed: false, port_pressure: [[1, '34'], [1, '012']]}
- {base: x, index: x, offset: imd, scale: 1, pre-indexed: false, post-indexed: true, port_pressure: [[1, '34'], [1, '012']]}
- {base: x, index: x, offset: imd, scale: 1, pre-indexed: false, post-indexed: false, port_pressure: [[1, '34'], [1, '012']]}
- {base: x, index: x, offset: imd, scale: 1, pre-indexed: true, post-indexed: true, port_pressure: [[1, '34'], [1, '012']]}
- {base: x, index: x, offset: imd, scale: 1, pre-indexed: true, post-indexed: false, port_pressure: [[1, '34'], [1, '012']]}
ports: ['0', '1', '2', '3', '4', '5', '6', '7']
port_model_scheme: |
+--------------------------------------------------------------------------------------------+
| - entries |
+--------------------------------------------------------------------------------------------+
0 |ALU 1 |AB 2 |AB 3 |MDU 4 |FSU1 5 |FSU2 6 |LdSt 7 |LdSt
\/ \/ \/ \/ \/ \/ \/ \/
+---------+ +---------+ +---------+ +-------------+ +-------+ +------ + +-------+ +-------+
| INT ALU | | INT ALU | | INT ALU | | Multi-Cycle | | FP | | FP | | LD/ST | | LD/ST |
+---------+ | BRU | | BRU | +-------------+ | ASIMD | | ASIMD | +-------+ +-------+
+---------+ +---------+ +-------+ +-------+
instruction_forms:
- name: add
operands:
- class: register
prefix: w
- class: register
prefix: w
- class: register
prefix: w
throughput: 0.3333
latency: 1.0 # 1*p012
port_pressure: [[1, '012']]
- name: ldur
operands:
- class: register
prefix: w
- class: memory
base: x
offset: imd
index: '*'
scale: '*'
post-indexed: false
pre-indexed: false
throughput: 0.5
latency: 4.0 # 1*p67
port_pressure: [[1, '67']]
- name: ldr
operands:
- class: register
prefix: w
- class: memory
base: x
offset: imd
index: '*'
scale: '*'
post-indexed: false
pre-indexed: false
throughput: 0.5
latency: 4.0 # 1*p67
port_pressure: [[1, '67']]
- name: str
operands:
- class: register
prefix: w
- class: memory
base: x
offset: imd
index: '*'
scale: '*'
post-indexed: false
pre-indexed: false
throughput: 0.5
latency: 1.0 # 1*p67
port_pressure: [[1, '67']]

3
osaca/osaca.py
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@@ -32,6 +32,7 @@ SUPPORTED_ARCHS = [
"TX2",
"N1",
"A64FX",
"TSV110",
"A72",
]
DEFAULT_ARCHS = {
@@ -96,7 +97,7 @@ def create_parser(parser=None):
"--arch",
type=str,
help="Define architecture (SNB, IVB, HSW, BDW, SKX, CSX, ICL, ZEN1, ZEN2, TX2, N1, "
"A64FX, A72). If no architecture is given, OSACA assumes a default uarch for x86/AArch64.",
"A64FX, TSV110, A72). If no architecture is given, OSACA assumes a default uarch for x86/AArch64.",
)
parser.add_argument(
"--fixed",

1
osaca/semantics/hw_model.py
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@@ -266,6 +266,7 @@ class MachineModel(object):
"""Return ISA for given micro-arch ``arch``."""
arch_dict = {
"a64fx": "aarch64",
"tsv110": "aarch64",
"a72": "aarch64",
"tx2": "aarch64",
"n1": "aarch64",