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tiny update in port model

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JanLJL
2019-12-20 16:23:18 +01:00
parent 7c1dc83658
commit 7a01a02b43
1 changed files with 1 additions and 1 deletions
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osaca/data/zen1.yml
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@@ -26,7 +26,7 @@ port_model_scheme: |
|SSE ALU| |SSE ALU| |SSE ALU| |SSE ALU| | ALU | | ALU | | ALU | | ALU | | AGU | | AGU |
└-------┘ └-------┘ └-------┘ └-------┘ └------┘ └-----┘ └-----┘ └------┘ └-----┘ └-----┘
┌-------┐ ┌-------┐ ┌-------┐ ┌-------┐ ┌------┐ ┌-----┐ ┌-----┐ ┌------┐ | |
|SSE MUL| |SSE MUL| |SSE ADD| |SSE ADD| |BRANCH| | MUL | | MUL | |BRANCH| ▼ ▼
|SSE MUL| |SSE MUL| |SSE ADD| |SSE ADD| |BRANCH| | MUL | | DIV | |BRANCH| ▼ ▼
└-------┘ └-------┘ └-------┘ └-------┘ └------┘ └-----┘ └-----┘ └------┘ ┌-------------┐
┌-------┐ ┌-------┐ ┌-------┐ ┌-------┐ | LOAD |
|SSE FMA| |SSE FMA| | SSE | |SSE DIV| └-------------┘