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Data for creating A72 model
Add PMEvo mapping from https://github.com/cdl-saarland/pmevo-artifact/blob/master/vm_setup/data/A72/mapping_pmevo.json together with a template file to allow generating an OSACA model for the A72.
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401
osaca/data/a72/mapping_pmevo.json
Normal file
401
osaca/data/a72/mapping_pmevo.json
Normal file
File diff suppressed because one or more lines are too long
808
osaca/data/a72/template.yml
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808
osaca/data/a72/template.yml
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@@ -0,0 +1,808 @@
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osaca_version: 0.3.11
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micro_architecture: Cortex A-72
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arch_code: a72
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isa: aarch64
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hidden_loads: false
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ports: ['0', '1', '2', '3', '4', '5', '6', '7']
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port_model_scheme: |
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+-------------------------------------------------------------------------------------+
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| scheduler |
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+-------------------------------------------------------------------------------------+
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0 |I 1 |L 2 |M 3 |S 4 |F1 5 |I 6 |F0 7 |B
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\/ \/ \/ \/ \/ \/ \/ \/
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+-------+ +-------+ +-------+ +-------+ +-----------+ +-------+ +---------+ +-------+
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|INT ALU| | LOAD | | MUL | | STORE | | ASIMD | |INT ALU| | ASIMD | | Branch|
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+-------+ +-------+ +-------+ +-------+ +-----------+ +-------+ +---------+ +-------+
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+-------+ +-------+ +-----------+ +-------+ +---------+
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| AGU | | DIV | | FP ALU | | AGU | |ASIMD MUL|
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+-------+ +-------+ +-----------+ +-------+ +---------+
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+-------+ +-----------+ +---------+
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| SHIFT | | FP MUL | | FP ALU |
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+-------+ +-----------+ +---------+
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+-------+ +-----------+ +---------+
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| CRC | | FP DIV | | FP MUL |
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+-------+ +-----------+ +---------+
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+-------+ +-----------+ +---------+
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| USAD | | FP SQRT | | FP DIV |
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+-------+ +-----------+ +---------+
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+-----------+ +---------+
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|ASIMD SHIFT| | FP CONV |
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+-----------+ +---------+
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+---------+
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| CRYPTO |
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+---------+
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# The port pressues do not always correctly match this schema, because most
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# instructions are imported from an experimentally determined mapping, which
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# is not always correct.
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load_latency: {x: 4.0, s: 5.0, d: 5.0, h: 6.0, q: 6.0}
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load_throughput: []
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load_throughput_default: [[1, '1']]
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store_throughput: []
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store_throughput_default: [[2, '3']]
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instruction_forms:
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# Branch
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- name: b
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operands:
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- class: identifier
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latency: 1.0
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port_pressure: [[1, '7']]
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throughput: 1.0
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- name: bne
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operands:
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- class: identifier
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latency: 1.0
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port_pressure: [[1, '7']]
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throughput: 1.0
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- name: b.ne
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operands:
|
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- class: identifier
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latency: 1.0
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port_pressure: [[1, '7']]
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throughput: 1.0
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- name: br
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operands:
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- class: register
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prefix: x
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latency: 1.0
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port_pressure: [[1, '7']]
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throughput: 1.0
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- name: ret
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operands:
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- class: register
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prefix: x
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latency: 1.0
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port_pressure: [[1, '7']]
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throughput: 1.0
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- name: bl
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operands:
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- class: identifier
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latency: 1.0
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port_pressure: [[1, '05'], [1, '7']]
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throughput: 1.0
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- name: blr
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operands:
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- class: register
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prefix: x
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latency: 1.0
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port_pressure: [[1, '05'], [1, '7']]
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throughput: 1.0
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# Load GPR
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- name: ldr
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operands:
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- class: register
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prefix: x
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- class: memory
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base: x
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offset: '*'
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index: '*'
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scale: '*'
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post-indexed: false
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pre-indexed: false
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latency: 4.0
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port_pressure: [[1, '1']]
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throughput: 1.0
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- name: ldr
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operands:
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- class: register
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prefix: x
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- class: memory
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base: x
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offset: '*'
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index: '*'
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scale: '*'
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post-indexed: true
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pre-indexed: false
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latency: 5.0
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port_pressure: [[1, '1'], [1, '05']]
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throughput: 1.0
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- name: ldr
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operands:
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- class: register
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prefix: x
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- class: memory
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base: x
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offset: '*'
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index: '*'
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scale: '*'
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post-indexed: false
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pre-indexed: true
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latency: 5.0
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port_pressure: [[1, '3'], [1, '05']]
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throughput: 1.0
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# Load FP d
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- name: ldr
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operands:
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- class: register
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prefix: d
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- class: memory
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base: x
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offset: '*'
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index: '*'
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scale: '*'
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post-indexed: false
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pre-indexed: false
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latency: 5.0
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port_pressure: [[1, '1']]
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throughput: 1.0
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- name: ldr
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operands:
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- class: register
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prefix: d
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- class: memory
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base: x
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offset: '*'
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index: '*'
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scale: '*'
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post-indexed: true
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pre-indexed: false
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latency: 5.0
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port_pressure: [[1, '1'], [2, '05']]
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throughput: 1.0
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- name: ldr
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operands:
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- class: register
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prefix: d
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- class: memory
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base: x
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offset: '*'
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index: '*'
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scale: '*'
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post-indexed: false
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pre-indexed: true
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latency: 5.0
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port_pressure: [[1, '1'], [2, '05']]
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throughput: 1.0
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# Load FP q
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- name: ldr
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operands:
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- class: register
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prefix: q
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- class: memory
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base: x
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offset: '*'
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index: '*'
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scale: 1
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post-indexed: false
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pre-indexed: false
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latency: 5.0
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||||
port_pressure: [[1, '1']]
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throughput: 1.0
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- name: ldr
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operands:
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- class: register
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prefix: q
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- class: memory
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base: x
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offset: '*'
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index: '*'
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scale: 1
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post-indexed: true
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pre-indexed: false
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latency: 5.0
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||||
port_pressure: [[1, '1'], [1, '05']]
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throughput: 1.0
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- name: ldr
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||||
operands:
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- class: register
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prefix: q
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- class: memory
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base: x
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offset: '*'
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index: '*'
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scale: 1
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||||
post-indexed: false
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||||
pre-indexed: true
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latency: 5.0
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port_pressure: [[1, '1'], [1, '05']]
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throughput: 1.0
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- name: ldr
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operands:
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- class: register
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prefix: q
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- class: memory
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||||
base: x
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offset: '*'
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index: '*'
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scale: '*'
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||||
post-indexed: false
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pre-indexed: false
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latency: 6.0
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port_pressure: [[1, '1'], [1, '05']]
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throughput: 1.0
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- name: ldr
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operands:
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- class: register
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prefix: q
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- class: memory
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||||
base: x
|
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offset: '*'
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index: '*'
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scale: '*'
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post-indexed: true
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pre-indexed: false
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latency: 6.0
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port_pressure: [[1, '1'], [2, '05']]
|
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throughput: 1.0
|
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- name: ldr
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||||
operands:
|
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- class: register
|
||||
prefix: q
|
||||
- class: memory
|
||||
base: x
|
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offset: '*'
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index: '*'
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scale: '*'
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||||
post-indexed: false
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||||
pre-indexed: true
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latency: 6.0
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port_pressure: [[1, '1'], [2, '05']]
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throughput: 1.0
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# Store GPR
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- name: str
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operands:
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- class: register
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prefix: x
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- class: memory
|
||||
base: x
|
||||
offset: '*'
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||||
index: '*'
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||||
scale: '*'
|
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post-indexed: false
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||||
pre-indexed: false
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||||
latency: 1.0
|
||||
port_pressure: [[1, '3']]
|
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throughput: 1.0
|
||||
- name: str
|
||||
operands:
|
||||
- class: register
|
||||
prefix: x
|
||||
- class: memory
|
||||
base: x
|
||||
offset: '*'
|
||||
index: '*'
|
||||
scale: '*'
|
||||
post-indexed: true
|
||||
pre-indexed: false
|
||||
latency: 1.0
|
||||
port_pressure: [[1, '3'], [1, '05']]
|
||||
throughput: 1.0
|
||||
- name: str
|
||||
operands:
|
||||
- class: register
|
||||
prefix: x
|
||||
- class: memory
|
||||
base: x
|
||||
offset: '*'
|
||||
index: '*'
|
||||
scale: '*'
|
||||
post-indexed: false
|
||||
pre-indexed: true
|
||||
latency: 1.0
|
||||
port_pressure: [[1, '3'], [1, '05']]
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throughput: 1.0
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||||
|
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# Store FP d
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||||
- name: str
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||||
operands:
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- class: register
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||||
prefix: d
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- class: memory
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||||
base: x
|
||||
offset: '*'
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||||
index: '*'
|
||||
scale: '*'
|
||||
post-indexed: false
|
||||
pre-indexed: false
|
||||
latency: 1.0
|
||||
port_pressure: [[1, '3'], [1, '05']]
|
||||
throughput: 1.0
|
||||
- name: str
|
||||
operands:
|
||||
- class: register
|
||||
prefix: d
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||||
- class: memory
|
||||
base: x
|
||||
offset: '*'
|
||||
index: '*'
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||||
scale: '*'
|
||||
post-indexed: true
|
||||
pre-indexed: false
|
||||
latency: 1.0
|
||||
port_pressure: [[1, '3'], [1, '05']]
|
||||
throughput: 1.0
|
||||
- name: str
|
||||
operands:
|
||||
- class: register
|
||||
prefix: d
|
||||
- class: memory
|
||||
base: x
|
||||
offset: '*'
|
||||
index: '*'
|
||||
scale: '*'
|
||||
post-indexed: false
|
||||
pre-indexed: true
|
||||
latency: 1.0
|
||||
port_pressure: [[1, '3'], [1, '05']]
|
||||
throughput: 1.0
|
||||
|
||||
# Store FP q
|
||||
- name: str
|
||||
operands:
|
||||
- class: register
|
||||
prefix: q
|
||||
- class: memory
|
||||
base: x
|
||||
offset: '*'
|
||||
index: '*'
|
||||
scale: 1
|
||||
post-indexed: false
|
||||
pre-indexed: false
|
||||
latency: 4.0
|
||||
port_pressure: [[2, '3']]
|
||||
throughput: 2.0
|
||||
- name: str
|
||||
operands:
|
||||
- class: register
|
||||
prefix: q
|
||||
- class: memory
|
||||
base: x
|
||||
offset: '*'
|
||||
index: '*'
|
||||
scale: 1
|
||||
post-indexed: true
|
||||
pre-indexed: false
|
||||
latency: 4.0
|
||||
port_pressure: [[2, '3'], [1, '05']]
|
||||
throughput: 2.0
|
||||
- name: str
|
||||
operands:
|
||||
- class: register
|
||||
prefix: q
|
||||
- class: memory
|
||||
base: x
|
||||
offset: '*'
|
||||
index: '*'
|
||||
scale: 1
|
||||
post-indexed: false
|
||||
pre-indexed: true
|
||||
latency: 2.0
|
||||
port_pressure: [[2, '3'], [1, '05']]
|
||||
throughput: 2.0
|
||||
- name: str
|
||||
operands:
|
||||
- class: register
|
||||
prefix: q
|
||||
- class: memory
|
||||
base: x
|
||||
offset: '*'
|
||||
index: '*'
|
||||
scale: '*'
|
||||
post-indexed: false
|
||||
pre-indexed: false
|
||||
latency: 4.0
|
||||
port_pressure: [[2, '3'], [1, '05']]
|
||||
throughput: 2.0
|
||||
- name: str
|
||||
operands:
|
||||
- class: register
|
||||
prefix: q
|
||||
- class: memory
|
||||
base: x
|
||||
offset: '*'
|
||||
index: '*'
|
||||
scale: '*'
|
||||
post-indexed: true
|
||||
pre-indexed: false
|
||||
latency: 4.0
|
||||
port_pressure: [[2, '3'], [2, '05']]
|
||||
throughput: 2.0
|
||||
- name: str
|
||||
operands:
|
||||
- class: register
|
||||
prefix: q
|
||||
- class: memory
|
||||
base: x
|
||||
offset: '*'
|
||||
index: '*'
|
||||
scale: '*'
|
||||
post-indexed: false
|
||||
pre-indexed: true
|
||||
latency: 4.0
|
||||
port_pressure: [[2, '3'], [2, '05']]
|
||||
throughput: 2.0
|
||||
|
||||
# Load unscaled GPR
|
||||
- name: ldur
|
||||
operands:
|
||||
- class: register
|
||||
prefix: x
|
||||
- class: memory
|
||||
base: x
|
||||
offset: '*'
|
||||
index: '*'
|
||||
scale: '*'
|
||||
post-indexed: '*'
|
||||
pre-indexed: '*'
|
||||
latency: 4.0
|
||||
port_pressure: [[1, '1']]
|
||||
throughput: 1.0
|
||||
|
||||
# Load unscaled FP q
|
||||
- name: ldur
|
||||
operands:
|
||||
- class: register
|
||||
prefix: q
|
||||
- class: memory
|
||||
base: x
|
||||
offset: '*'
|
||||
index: '*'
|
||||
scale: '*'
|
||||
post-indexed: '*'
|
||||
pre-indexed: '*'
|
||||
latency: 5.0
|
||||
port_pressure: [[1, '1']]
|
||||
throughput: 1.0
|
||||
|
||||
# Store unscaled GPR
|
||||
- name: stur
|
||||
operands:
|
||||
- class: register
|
||||
prefix: x
|
||||
- class: memory
|
||||
base: x
|
||||
offset: '*'
|
||||
index: '*'
|
||||
scale: '*'
|
||||
post-indexed: '*'
|
||||
pre-indexed: '*'
|
||||
latency: 1.0
|
||||
port_pressure: [[1, '3']]
|
||||
throughput: 1.0
|
||||
|
||||
# Store unscaled FP q
|
||||
- name: stur
|
||||
operands:
|
||||
- class: register
|
||||
prefix: q
|
||||
- class: memory
|
||||
base: x
|
||||
offset: '*'
|
||||
index: '*'
|
||||
scale: '*'
|
||||
post-indexed: '*'
|
||||
pre-indexed: '*'
|
||||
latency: 2.0
|
||||
port_pressure: [[2, '3']]
|
||||
throughput: 2.0
|
||||
|
||||
# Load pair GPR
|
||||
- name: ldp
|
||||
operands:
|
||||
- class: register
|
||||
prefix: x
|
||||
- class: register
|
||||
prefix: x
|
||||
- class: memory
|
||||
base: x
|
||||
offset: '*'
|
||||
index: '*'
|
||||
scale: '*'
|
||||
post-indexed: false
|
||||
pre-indexed: false
|
||||
latency: 4.0
|
||||
port_pressure: [[1, '1']]
|
||||
throughput: 1.0
|
||||
- name: ldp
|
||||
operands:
|
||||
- class: register
|
||||
prefix: x
|
||||
- class: register
|
||||
prefix: x
|
||||
- class: memory
|
||||
base: x
|
||||
offset: '*'
|
||||
index: '*'
|
||||
scale: '*'
|
||||
post-indexed: true
|
||||
pre-indexed: false
|
||||
latency: 4.0
|
||||
port_pressure: [[1, '1'], [1, '05']]
|
||||
throughput: 1.0
|
||||
- name: ldp
|
||||
operands:
|
||||
- class: register
|
||||
prefix: x
|
||||
- class: register
|
||||
prefix: x
|
||||
- class: memory
|
||||
base: x
|
||||
offset: '*'
|
||||
index: '*'
|
||||
scale: '*'
|
||||
post-indexed: false
|
||||
pre-indexed: true
|
||||
latency: 4.0
|
||||
port_pressure: [[1, '1'], [1, '05']]
|
||||
throughput: 1.0
|
||||
|
||||
# Load pair FP q
|
||||
- name: ldp
|
||||
operands:
|
||||
- class: register
|
||||
prefix: q
|
||||
- class: register
|
||||
prefix: q
|
||||
- class: memory
|
||||
base: x
|
||||
offset: '*'
|
||||
index: '*'
|
||||
scale: '*'
|
||||
post-indexed: false
|
||||
pre-indexed: false
|
||||
latency: 6.0
|
||||
port_pressure: [[2, '1']]
|
||||
throughput: 2.0
|
||||
- name: ldp
|
||||
operands:
|
||||
- class: register
|
||||
prefix: q
|
||||
- class: register
|
||||
prefix: q
|
||||
- class: memory
|
||||
base: x
|
||||
offset: '*'
|
||||
index: '*'
|
||||
scale: '*'
|
||||
post-indexed: true
|
||||
pre-indexed: false
|
||||
latency: 6.0
|
||||
port_pressure: [[2, '1'], [1, '05']]
|
||||
throughput: 2.0
|
||||
- name: ldp
|
||||
operands:
|
||||
- class: register
|
||||
prefix: q
|
||||
- class: register
|
||||
prefix: q
|
||||
- class: memory
|
||||
base: x
|
||||
offset: '*'
|
||||
index: '*'
|
||||
scale: '*'
|
||||
post-indexed: false
|
||||
pre-indexed: true
|
||||
latency: 6.0
|
||||
port_pressure: [[2, '1'], [1, '05']]
|
||||
throughput: 2.0
|
||||
|
||||
# Store pair GPR
|
||||
- name: stp
|
||||
operands:
|
||||
- class: register
|
||||
prefix: x
|
||||
- class: register
|
||||
prefix: x
|
||||
- class: memory
|
||||
base: x
|
||||
offset: '*'
|
||||
index: '*'
|
||||
scale: '*'
|
||||
post-indexed: false
|
||||
pre-indexed: false
|
||||
latency: 2.0
|
||||
port_pressure: [[2, '3']]
|
||||
throughput: 2.0
|
||||
- name: stp
|
||||
operands:
|
||||
- class: register
|
||||
prefix: x
|
||||
- class: register
|
||||
prefix: x
|
||||
- class: memory
|
||||
base: x
|
||||
offset: '*'
|
||||
index: '*'
|
||||
scale: '*'
|
||||
post-indexed: true
|
||||
pre-indexed: false
|
||||
latency: 2.0
|
||||
port_pressure: [[2, '3'], [1, '05']]
|
||||
throughput: 2.0
|
||||
- name: stp
|
||||
operands:
|
||||
- class: register
|
||||
prefix: x
|
||||
- class: register
|
||||
prefix: x
|
||||
- class: memory
|
||||
base: x
|
||||
offset: '*'
|
||||
index: '*'
|
||||
scale: '*'
|
||||
post-indexed: false
|
||||
pre-indexed: true
|
||||
latency: 2.0
|
||||
port_pressure: [[2, '3'], [1, '05']]
|
||||
throughput: 2.0
|
||||
|
||||
# Store pair FP q
|
||||
- name: stp
|
||||
operands:
|
||||
- class: register
|
||||
prefix: q
|
||||
- class: register
|
||||
prefix: q
|
||||
- class: memory
|
||||
base: x
|
||||
offset: '*'
|
||||
index: '*'
|
||||
scale: '*'
|
||||
post-indexed: false
|
||||
pre-indexed: false
|
||||
latency: 4.0
|
||||
port_pressure: [[4, '3'], [1, '05']]
|
||||
throughput: 4.0
|
||||
- name: stp
|
||||
operands:
|
||||
- class: register
|
||||
prefix: q
|
||||
- class: register
|
||||
prefix: q
|
||||
- class: memory
|
||||
base: x
|
||||
offset: '*'
|
||||
index: '*'
|
||||
scale: '*'
|
||||
post-indexed: true
|
||||
pre-indexed: false
|
||||
latency: 4.0
|
||||
port_pressure: [[4, '3'], [1, '05']]
|
||||
throughput: 4.0
|
||||
- name: stp
|
||||
operands:
|
||||
- class: register
|
||||
prefix: q
|
||||
- class: register
|
||||
prefix: q
|
||||
- class: memory
|
||||
base: x
|
||||
offset: '*'
|
||||
index: '*'
|
||||
scale: '*'
|
||||
post-indexed: false
|
||||
pre-indexed: true
|
||||
latency: 4.0
|
||||
port_pressure: [[4, '3'], [1, '05']]
|
||||
throughput: 4.0
|
||||
|
||||
# Fast-forward (measures 4 cycles, but can be 3)
|
||||
# Lower bound is used in order to ensure no over-estimates are possible.
|
||||
# Ports do not match documentation, but "fixing" requires also "fixing" almost
|
||||
# the entire rest of the model.
|
||||
- name: fadd
|
||||
operands:
|
||||
- class: register
|
||||
prefix: s
|
||||
- class: register
|
||||
prefix: s
|
||||
- class: register
|
||||
prefix: s
|
||||
latency: 3.0
|
||||
port_pressure: [[1, '45']]
|
||||
throughput: 0.5
|
||||
- name: fadd
|
||||
operands:
|
||||
- class: register
|
||||
prefix: d
|
||||
- class: register
|
||||
prefix: d
|
||||
- class: register
|
||||
prefix: d
|
||||
latency: 3.0
|
||||
port_pressure: [[1, '45']]
|
||||
throughput: 0.5
|
||||
- name: fadd
|
||||
operands:
|
||||
- class: register
|
||||
prefix: v
|
||||
shape: s
|
||||
- class: register
|
||||
prefix: v
|
||||
shape: s
|
||||
- class: register
|
||||
prefix: v
|
||||
shape: s
|
||||
latency: 3.0
|
||||
port_pressure: [[1, '5']]
|
||||
throughput: 1.0
|
||||
- name: fadd
|
||||
operands:
|
||||
- class: register
|
||||
prefix: v
|
||||
shape: d
|
||||
- class: register
|
||||
prefix: v
|
||||
shape: d
|
||||
- class: register
|
||||
prefix: v
|
||||
shape: d
|
||||
latency: 3.0
|
||||
port_pressure: [[1, '5']]
|
||||
throughput: 1.0
|
||||
- name: fsub
|
||||
operands:
|
||||
- class: register
|
||||
prefix: s
|
||||
- class: register
|
||||
prefix: s
|
||||
- class: register
|
||||
prefix: s
|
||||
latency: 3.0
|
||||
port_pressure: [[1, '45']]
|
||||
throughput: 0.5
|
||||
- name: fsub
|
||||
operands:
|
||||
- class: register
|
||||
prefix: d
|
||||
- class: register
|
||||
prefix: d
|
||||
- class: register
|
||||
prefix: d
|
||||
latency: 3.0
|
||||
port_pressure: [[1, '45']]
|
||||
throughput: 0.5
|
||||
- name: fsub
|
||||
operands:
|
||||
- class: register
|
||||
prefix: v
|
||||
shape: s
|
||||
- class: register
|
||||
prefix: v
|
||||
shape: s
|
||||
- class: register
|
||||
prefix: v
|
||||
shape: s
|
||||
latency: 3.0
|
||||
port_pressure: [[1, '5']]
|
||||
throughput: 1.0
|
||||
- name: fsub
|
||||
operands:
|
||||
- class: register
|
||||
prefix: v
|
||||
shape: d
|
||||
- class: register
|
||||
prefix: v
|
||||
shape: d
|
||||
- class: register
|
||||
prefix: v
|
||||
shape: d
|
||||
latency: 3.0
|
||||
port_pressure: [[1, '5']]
|
||||
throughput: 1.0
|
||||
|
||||
# Automatically generated instructions
|
||||
Reference in New Issue
Block a user