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JanLJL
2021-10-14 10:59:55 +02:00
parent be891d45d4
commit 9c16f8bc56
2 changed files with 38 additions and 38 deletions
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30
osaca/osaca.py
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@@ -20,19 +20,19 @@ from osaca.semantics import (
SUPPORTED_ARCHS = [
'SNB',
'IVB',
'HSW',
'BDW',
'SKX',
'CSX',
'ICL',
'ZEN1',
'ZEN2',
'TX2',
'N1',
'A64FX',
'A72',
"SNB",
"IVB",
"HSW",
"BDW",
"SKX",
"CSX",
"ICL",
"ZEN1",
"ZEN2",
"TX2",
"N1",
"A64FX",
"A72",
]
DEFAULT_ARCHS = {
"aarch64": "A64FX",
@@ -95,8 +95,8 @@ def create_parser(parser=None):
parser.add_argument(
"--arch",
type=str,
help='Define architecture (SNB, IVB, HSW, BDW, SKX, CSX, ICL, ZEN1, ZEN2, TX2, N1, '
'A64FX, A72). If no architecture is given, OSACA assumes a default uarch for x86/AArch64.',
help="Define architecture (SNB, IVB, HSW, BDW, SKX, CSX, ICL, ZEN1, ZEN2, TX2, N1, "
"A64FX, A72). If no architecture is given, OSACA assumes a default uarch for x86/AArch64.",
)
parser.add_argument(
"--fixed",

46
osaca/semantics/hw_model.py
View File

@@ -265,29 +265,29 @@ class MachineModel(object):
def get_isa_for_arch(arch):
"""Return ISA for given micro-arch ``arch``."""
arch_dict = {
'a64fx': 'aarch64',
'a72': 'aarch64',
'tx2': 'aarch64',
'n1': 'aarch64',
'zen1': 'x86',
'zen+': 'x86',
'zen2': 'x86',
'icl': 'x86',
'con': 'x86', # Intel Conroe
'wol': 'x86', # Intel Wolfdale
'snb': 'x86',
'ivb': 'x86',
'hsw': 'x86',
'bdw': 'x86',
'skl': 'x86',
'skx': 'x86',
'csx': 'x86',
'wsm': 'x86',
'nhm': 'x86',
'kbl': 'x86',
'cnl': 'x86',
'cfl': 'x86',
'icl': 'x86',
"a64fx": "aarch64",
"a72": "aarch64",
"tx2": "aarch64",
"n1": "aarch64",
"zen1": "x86",
"zen+": "x86",
"zen2": "x86",
"icl": "x86",
"con": "x86", # Intel Conroe
"wol": "x86", # Intel Wolfdale
"snb": "x86",
"ivb": "x86",
"hsw": "x86",
"bdw": "x86",
"skl": "x86",
"skx": "x86",
"csx": "x86",
"wsm": "x86",
"nhm": "x86",
"kbl": "x86",
"cnl": "x86",
"cfl": "x86",
"icl": "x86",
}
arch = arch.lower()
if arch in arch_dict: