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JanLJL
2021-10-14 09:23:35 +02:00
parent 12044e3ac4
commit ab368cded1
1 changed files with 5 additions and 6 deletions
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osaca/data/a72.yml
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@@ -3,6 +3,11 @@ micro_architecture: Cortex A-72
arch_code: a72
isa: aarch64
hidden_loads: false
load_latency: {x: 4.0, s: 5.0, d: 5.0, h: 6.0, q: 6.0}
load_throughput: []
load_throughput_default: [[1, '1']]
store_throughput: []
store_throughput_default: [[2, '3']]
ports: ['0', '1', '2', '3', '4', '5', '6', '7']
port_model_scheme: |
+-------------------------------------------------------------------------------------+
@@ -31,13 +36,7 @@ port_model_scheme: |
+---------+
| CRYPTO |
+---------+
load_latency: {x: 4.0, s: 5.0, d: 5.0, h: 6.0, q: 6.0}
load_throughput_default: [[1, '1']]
store_throughput: []
store_throughput_default: [[2, '3']]
load_throughput: []
instruction_forms:
# Branch
- name: B
operands: