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Merge pull request #48 from RRZE-HPC/n1
initial implementation of Neoverse N1 support
This commit is contained in:
Jan
GitHub
771
osaca/data/n1.yml
Normal file
771
osaca/data/n1.yml
Normal file
@@ -0,0 +1,771 @@
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osaca_version: 0.3.3
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micro_architecture: Arm Neoverse N1
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arch_code: n1
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isa: AArch64
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ROB_size: 128 # wikichip
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retired_uOps_per_cycle: 8 # wikichip
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scheduler_size: 120 # wikichip
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hidden_loads: false
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load_latency: {w: 4.0, x: 4.0, b: 4.0, h: 4.0, s: 4.0, d: 5.0, q: 6.0, v: 5.0, z: 4.0}
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load_throughput:
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- {base: x, index: ~, offset: ~, scale: 1, pre-indexed: false, post-indexed: false, port_pressure: [[1, '67']]}
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- {base: x, index: ~, offset: imd, scale: 1, pre-indexed: false, post-indexed: true, port_pressure: [[1, '67'], [1, '123']]}
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||||
- {base: x, index: ~, offset: imd, scale: 1, pre-indexed: false, post-indexed: false, port_pressure: [[1, '67']]}
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||||
- {base: x, index: ~, offset: imd, scale: 1, pre-indexed: true, post-indexed: true, port_pressure: [[1, '67'], [1, '123']]}
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||||
- {base: x, index: ~, offset: imd, scale: 1, pre-indexed: true, post-indexed: false, port_pressure: [[1, '67'], [1, '123']]}
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- {base: x, index: x, offset: ~, scale: 1, pre-indexed: false, post-indexed: true, port_pressure: [[1, '67'], [1, '123']]}
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- {base: x, index: x, offset: ~, scale: 1, pre-indexed: false, post-indexed: false, port_pressure: [[1, '67']]}
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- {base: x, index: x, offset: ~, scale: 1, pre-indexed: true, post-indexed: true, port_pressure: [[1, '67'], [1, '123']]}
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- {base: x, index: x, offset: ~, scale: 1, pre-indexed: true, post-indexed: false, port_pressure: [[1, '67'], [1, '123']]}
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- {base: x, index: x, offset: imd, scale: 1, pre-indexed: false, post-indexed: true, port_pressure: [[1, '67'], [1, '123']]}
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- {base: x, index: x, offset: imd, scale: 1, pre-indexed: false, post-indexed: false, port_pressure: [[1, '67']]}
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- {base: x, index: x, offset: imd, scale: 1, pre-indexed: true, post-indexed: true, port_pressure: [[1, '67'], [1, '123']]}
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- {base: x, index: x, offset: imd, scale: 1, pre-indexed: true, post-indexed: false, port_pressure: [[1, '67'], [1, '123']]}
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load_throughput_default: [[1, '67']]
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store_throughput: []
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store_throughput_default: [[1, '56'], [1, '67']]
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ports: ['0', '1', '2', '3', '4', '4DV', '5', '6', '7']
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port_model_scheme: |
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+----------------------------------------------------------------------------+
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| 120 entries |
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+----------------------------------------------------------------------------+
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0 |BR 1 |IS0 2 |IS1 3 |IM0 4 |FP0 5 |FP1 6 |LDST 7 |LDST
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\/ \/ \/ \/ \/ \/ \/ \/
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+------+ +-----+ +-----+ +-----+ +--------+ +--------+ +-------+ +-------+
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|Branch| | INT | | INT | | INT | | FP ALU | | FP ALU | | AGU | | AGU |
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+------+ | ALU | | ALU | | ALU | +--------+ +--------+ +-------+ +-------+
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+-----+ +-----+ +-----+ +--------+ +--------+ +-------+ +-------+
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+-----+ +-----+ | FP MUL | | FP MUL | |LD DATA| |LD DATA|
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| ST | | INT | +--------+ +--------+ +-------+ +-------+
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| INT | | MUL | +--------+ +---------+
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+-----+ +-----+ | FP DIV | |SIMD SHFT|
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+-----+ +--------+ +---------+
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| INT | +--------+ +--------+
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| DIV | | FMA | | FMA |
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+-----+ +--------+ +--------+
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+-----+ +--------+ +--------+
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|SHIFT| | ST SIMD| | ST SIMD|
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+-----+ | DATA | | DATA |
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+-----+ +--------+ +--------+
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| ST |
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| INT |
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+-----+
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instruction_forms:
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- name: add
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operands:
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- class: register
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prefix: x
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- class: register
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prefix: x
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- class: register
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prefix: x
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throughput: 0.33333333
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latency: 1.0 # 1*p123
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port_pressure: [[1, '123']]
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- name: add
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operands:
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- class: register
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prefix: x
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- class: register
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prefix: x
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- class: immediate
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imd: int
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throughput: 0.33333333
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latency: 1.0 # 1*p123
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port_pressure: [[1, '123']]
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- name: adds
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operands:
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- class: register
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prefix: x
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- class: register
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||||
prefix: x
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||||
- class: immediate
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imd: int
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throughput: 0.33333333
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||||
latency: 1.0 # 1*p123
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||||
port_pressure: [[1, '132']]
|
||||
- name: b.ne
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||||
operands:
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||||
- class: identifier
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||||
throughput: 1.0
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||||
latency: 0.0
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||||
port_pressure: [[1, '0']]
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||||
- name: b.gt
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||||
operands:
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- class: identifier
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||||
throughput: 1.0
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||||
latency: 0.0
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||||
port_pressure: [[1, '0']]
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||||
- name: bne
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||||
operands:
|
||||
- class: identifier
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||||
throughput: 1.0
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||||
latency: 0.0
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||||
port_pressure: [[1, '0']]
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- name: cmp
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operands:
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- class: register
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prefix: w
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- class: immediate
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||||
imd: int
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||||
throughput: 0.33333333
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||||
latency: 1.0 # 1*p123
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port_pressure: [[1, '123']]
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- name: cmp
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||||
operands:
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- class: register
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prefix: x
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||||
- class: register
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prefix: x
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throughput: 0.3333333
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latency: 1.0 # 1*p123
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port_pressure: [[1, '123']]
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||||
- name: dup
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operands:
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- class: register
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||||
prefix: d
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- class: register
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||||
prefix: v
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shape: d
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width: '*'
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throughput: 0.5
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latency: 2.0 # 1*p45
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port_pressure: [[1, '45']]
|
||||
- name: fadd
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operands:
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- class: register
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||||
prefix: v
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||||
shape: s
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||||
width: '*'
|
||||
- class: register
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||||
prefix: v
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||||
shape: s
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width: '*'
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- class: register
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||||
prefix: v
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shape: s
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width: '*'
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||||
throughput: 0.5
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||||
latency: 2.0 # 1*p45
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||||
port_pressure: [[1, '45']]
|
||||
- name: fadd
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operands:
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- class: register
|
||||
prefix: d
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width: '*'
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||||
- class: register
|
||||
prefix: d
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width: '*'
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- class: register
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||||
prefix: d
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width: '*'
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throughput: 0.5
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||||
latency: 2.0 # 1*p45
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||||
port_pressure: [[1, '45']]
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||||
- name: fadd
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||||
operands:
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- class: register
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||||
prefix: v
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shape: d
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width: '*'
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- class: register
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prefix: v
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shape: d
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width: '*'
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||||
- class: register
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prefix: v
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shape: d
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width: '*'
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throughput: 0.5
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latency: 2.0 # 1*p45
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port_pressure: [[1, '45']]
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- name: fdiv
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operands:
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- class: register
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prefix: v
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shape: s
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width: 128
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- class: register
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prefix: v
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shape: s
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width: 128
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||||
- class: register
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prefix: v
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shape: s
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width: 128
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throughput: 6.0
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latency: 8.0 # 1*p4+6*p4DV
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port_pressure: [[1, '4'], [6, [4DV]]]
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- name: fdiv
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operands:
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- class: register
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prefix: v
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shape: d
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width: 128
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||||
- class: register
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prefix: v
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shape: d
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width: 128
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- class: register
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prefix: v
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shape: d
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width: 128
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throughput: 10.0
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latency: 12.0 # 1*p4+10*p4DV
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port_pressure: [[4, '0'], [10, [4DV]]]
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- name: fmla
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operands:
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- class: register
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prefix: v
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shape: s
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width: '*'
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- class: register
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prefix: v
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shape: s
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width: '*'
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- class: register
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prefix: v
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shape: s
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||||
width: '*'
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throughput: 0.5
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latency: 2.0 # 1*p45
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port_pressure: [[1, '45']]
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- name: fmla
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operands:
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- class: register
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prefix: v
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shape: d
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width: '*'
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- class: register
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prefix: v
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shape: d
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width: '*'
|
||||
- class: register
|
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prefix: v
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shape: d
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||||
width: '*'
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throughput: 0.5
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latency: 2.0 # 1*p45
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port_pressure: [[1, '45']]
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- name: fmov
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operands:
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- {class: register, prefix: s}
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- {class: immediate, imd: double}
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latency: ~ # 1*p45
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port_pressure: [[1, '45']]
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throughput: 0.5
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- name: fmul
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operands:
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- class: register
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prefix: v
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shape: s
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width: '*'
|
||||
- class: register
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||||
prefix: v
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||||
shape: s
|
||||
width: '*'
|
||||
- class: register
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||||
prefix: v
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||||
shape: s
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||||
width: '*'
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||||
throughput: 0.5
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||||
latency: 3.0 # 1*p45
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||||
port_pressure: [[1, '45']]
|
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- name: fmul
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operands:
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- class: register
|
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prefix: v
|
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shape: d
|
||||
width: '*'
|
||||
- class: register
|
||||
prefix: v
|
||||
shape: d
|
||||
width: '*'
|
||||
- class: register
|
||||
prefix: v
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||||
shape: d
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||||
width: '*'
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throughput: 0.5
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latency: 3.0 # 1*p45
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port_pressure: [[1, '45']]
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- name: fmul
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operands:
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- class: register
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prefix: d
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- class: register
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prefix: d
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- class: register
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prefix: d
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throughput: 0.5
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latency: 3.0 # 1*p45
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port_pressure: [[1, '45']]
|
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- name: frecpe
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operands:
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- class: register
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||||
prefix: v
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||||
shape: s
|
||||
width: '*'
|
||||
- class: register
|
||||
prefix: v
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||||
shape: s
|
||||
width: '*'
|
||||
- class: register
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prefix: v
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shape: s
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width: '*'
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throughput: 2.0
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latency: 4.0 # 1*p4
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port_pressure: [[2, '4']]
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- name: frecpe
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operands:
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- class: register
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prefix: v
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||||
shape: d
|
||||
width: '*'
|
||||
- class: register
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||||
prefix: v
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shape: d
|
||||
width: '*'
|
||||
- class: register
|
||||
prefix: v
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shape: d
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||||
width: '*'
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throughput: 1.0
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||||
latency: 3.0 # 1*p4
|
||||
port_pressure: [[1, '4']]
|
||||
- name: fsub
|
||||
operands:
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||||
- class: register
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||||
prefix: v
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||||
shape: s
|
||||
width: '*'
|
||||
- class: register
|
||||
prefix: v
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||||
shape: s
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||||
width: '*'
|
||||
- class: register
|
||||
prefix: v
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||||
shape: s
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||||
width: '*'
|
||||
throughput: 0.5
|
||||
latency: 2.0 # 1*p45
|
||||
port_pressure: [[1, '45']]
|
||||
- name: fsub
|
||||
operands:
|
||||
- class: register
|
||||
prefix: v
|
||||
shape: d
|
||||
width: '*'
|
||||
- class: register
|
||||
prefix: v
|
||||
shape: d
|
||||
width: '*'
|
||||
- class: register
|
||||
prefix: v
|
||||
shape: d
|
||||
width: '*'
|
||||
throughput: 0.5
|
||||
latency: 2.0 # 1*p45
|
||||
port_pressure: [[1, '45']]
|
||||
- name: ldp
|
||||
operands:
|
||||
- class: register
|
||||
prefix: d
|
||||
- class: register
|
||||
prefix: d
|
||||
- class: memory
|
||||
base: x
|
||||
offset: imd
|
||||
index: ~
|
||||
scale: 1
|
||||
pre-indexed: false
|
||||
post-indexed: false
|
||||
throughput: 1.0
|
||||
latency: 5.0 # 2*p67, from n1 opt guide
|
||||
port_pressure: [[2, '67']]
|
||||
- name: ldp
|
||||
operands:
|
||||
- class: register
|
||||
prefix: d
|
||||
- class: register
|
||||
prefix: d
|
||||
- class: memory
|
||||
base: x
|
||||
offset: imd
|
||||
index: ~
|
||||
scale: 1
|
||||
pre-indexed: false
|
||||
post-indexed: true
|
||||
throughput: 1.0
|
||||
latency: 5.0 # 2*p67+1*p123, from n1 opt guide
|
||||
port_pressure: [[2, '67'], [1, '123']]
|
||||
- name: ldp
|
||||
operands:
|
||||
- class: register
|
||||
prefix: q
|
||||
- class: register
|
||||
prefix: q
|
||||
- class: memory
|
||||
base: x
|
||||
offset: '*'
|
||||
index: '*'
|
||||
scale: 1
|
||||
pre-indexed: false
|
||||
post-indexed: false
|
||||
throughput: 1.0
|
||||
latency: 7.0 # 2*p67, from n1 opt guide
|
||||
port_pressure: [[2, '67']]
|
||||
- name: ldp
|
||||
operands:
|
||||
- class: register
|
||||
prefix: q
|
||||
- class: register
|
||||
prefix: q
|
||||
- class: memory
|
||||
base: x
|
||||
offset: ~
|
||||
index: ~
|
||||
scale: 1
|
||||
pre-indexed: false
|
||||
post-indexed: true
|
||||
throughput: 1.0
|
||||
latency: 7.0 # 2*p67+1*p123, from n1 opt guide
|
||||
port_pressure: [[2, '56'], [1, '123']]
|
||||
- name: ldp
|
||||
operands:
|
||||
- class: register
|
||||
prefix: q
|
||||
- class: register
|
||||
prefix: q
|
||||
- class: memory
|
||||
base: x
|
||||
offset: '*'
|
||||
index: '*'
|
||||
scale: '*'
|
||||
pre-indexed: false
|
||||
post-indexed: false
|
||||
throughput: 1.0
|
||||
latency: 7.0 # 2*p67
|
||||
port_pressure: [[2, '67']]
|
||||
- name: ldp
|
||||
operands:
|
||||
- class: register
|
||||
prefix: q
|
||||
- class: register
|
||||
prefix: q
|
||||
- class: memory
|
||||
base: x
|
||||
offset: '*'
|
||||
index: '*'
|
||||
scale: '*'
|
||||
pre-indexed: true
|
||||
post-indexed: false
|
||||
throughput: 1.0
|
||||
latency: 7.0 # 2*p67+1*p123
|
||||
port_pressure: [[2, '67'], [1, '123']]
|
||||
- name: ldp
|
||||
operands:
|
||||
- class: register
|
||||
prefix: d
|
||||
- class: register
|
||||
prefix: d
|
||||
- class: memory
|
||||
base: x
|
||||
offset: '*'
|
||||
index: '*'
|
||||
scale: '*'
|
||||
pre-indexed: false
|
||||
post-indexed: true
|
||||
throughput: 1.0
|
||||
latency: 5.0 # 2*p67+1*p123
|
||||
port_pressure: [[2, '67'], [1, '123']]
|
||||
- name: ldur # JL: assumed from n1 opt guide
|
||||
operands:
|
||||
- class: register
|
||||
prefix: q
|
||||
- class: memory
|
||||
base: x
|
||||
offset: '*'
|
||||
index: '*'
|
||||
scale: '*'
|
||||
post-indexed: false
|
||||
pre-indexed: false
|
||||
throughput: 0.5
|
||||
latency: 6.0 # 1*p67
|
||||
port_pressure: [[1, '67']]
|
||||
- name: ldr
|
||||
operands:
|
||||
- class: register
|
||||
prefix: q
|
||||
- class: memory
|
||||
base: x
|
||||
offset: '*'
|
||||
index: '*'
|
||||
scale: '*'
|
||||
post-indexed: false
|
||||
pre-indexed: false
|
||||
throughput: 0.5
|
||||
latency: 6.0 # 1*p67
|
||||
port_pressure: [[1, '67']]
|
||||
- name: ldr
|
||||
operands:
|
||||
- class: register
|
||||
prefix: d
|
||||
- class: memory
|
||||
base: x
|
||||
offset: '*'
|
||||
index: '*'
|
||||
scale: '*'
|
||||
post-indexed: false
|
||||
pre-indexed: false
|
||||
throughput: 0.5
|
||||
latency: 5.0 # 1*p67
|
||||
port_pressure: [[1, '67']]
|
||||
- name: ldr
|
||||
operands:
|
||||
- class: register
|
||||
prefix: d
|
||||
- class: memory
|
||||
base: x
|
||||
offset: imd
|
||||
index: '*'
|
||||
scale: '*'
|
||||
post-indexed: false
|
||||
pre-indexed: false
|
||||
throughput: 0.5
|
||||
latency: 5.0 # 1*p67
|
||||
port_pressure: [[1, '67']]
|
||||
- name: ldr
|
||||
operands:
|
||||
- class: register
|
||||
prefix: d
|
||||
- class: memory
|
||||
base: x
|
||||
offset: '*'
|
||||
index: '*'
|
||||
scale: '*'
|
||||
post-indexed: false
|
||||
pre-indexed: false
|
||||
throughput: 0.5
|
||||
latency: 5.0 # 1*p67
|
||||
port_pressure: [[1, '67']]
|
||||
- name: ldr
|
||||
operands:
|
||||
- class: register
|
||||
prefix: x
|
||||
- class: register
|
||||
prefix: x
|
||||
throughput: 0.0
|
||||
latency: 0.0
|
||||
port_pressure: []
|
||||
- name: ldr
|
||||
operands:
|
||||
- class: register
|
||||
prefix: q
|
||||
- class: register
|
||||
prefix: q
|
||||
throughput: 0.0
|
||||
latency: 0.0
|
||||
port_pressure: []
|
||||
- name: ldr
|
||||
operands:
|
||||
- class: register
|
||||
prefix: d
|
||||
- class: register
|
||||
prefix: d
|
||||
throughput: 0.0
|
||||
latency: 0.0
|
||||
port_pressure: []
|
||||
- name: mov
|
||||
operands:
|
||||
- class: register
|
||||
prefix: x
|
||||
- class: register
|
||||
prefix: x
|
||||
throughput: 0.25
|
||||
latency: 1.0 # 1*p3456
|
||||
port_pressure: [[1, '3456']]
|
||||
- name: mov
|
||||
operands:
|
||||
- class: register
|
||||
prefix: v
|
||||
shape: b
|
||||
width: '*'
|
||||
- class: register
|
||||
prefix: v
|
||||
shape: b
|
||||
width: '*'
|
||||
throughput: 0.5
|
||||
latency: 2.0 # 1*p45
|
||||
port_pressure: [[1, '45']]
|
||||
- name: stp
|
||||
operands:
|
||||
- class: register
|
||||
prefix: d
|
||||
- class: register
|
||||
prefix: d
|
||||
- class: memory
|
||||
base: x
|
||||
offset: '*'
|
||||
index: '*'
|
||||
scale: '*'
|
||||
pre-indexed: false
|
||||
post-indexed: false
|
||||
throughput: 1.0
|
||||
latency: 0 # 2*p45+1*p67
|
||||
port_pressure: [[2, '45'], [1, '67']]
|
||||
- name: stp
|
||||
operands:
|
||||
- class: register
|
||||
prefix: q
|
||||
- class: register
|
||||
prefix: q
|
||||
- class: memory
|
||||
base: x
|
||||
offset: '*'
|
||||
index: '*'
|
||||
scale: '*'
|
||||
pre-indexed: false
|
||||
post-indexed: true
|
||||
throughput: 1.0
|
||||
latency: 0 # 2*p45+2*p67+1*123
|
||||
port_pressure: [[2, '45'], [2, '67'], [1, '123']]
|
||||
- name: stp
|
||||
operands:
|
||||
- class: register
|
||||
prefix: q
|
||||
- class: register
|
||||
prefix: q
|
||||
- class: memory
|
||||
base: x
|
||||
offset: '*'
|
||||
index: '*'
|
||||
scale: '*'
|
||||
pre-indexed: false
|
||||
post-indexed: false
|
||||
throughput: 1.0
|
||||
latency: 0 # 2*p45+2*p67
|
||||
port_pressure: [[2, '45'], [2, '67']]
|
||||
- name: stur # JL: assumed from n1 opt guide
|
||||
operands:
|
||||
- class: register
|
||||
prefix: d
|
||||
- class: memory
|
||||
base: x
|
||||
offset: '*'
|
||||
index: '*'
|
||||
scale: '*'
|
||||
pre-indexed: false
|
||||
post-indexed: false
|
||||
throughput: 0.5
|
||||
latency: 0 # 1*p67+1*p23
|
||||
port_pressure: [[1, '56'], [1, '23']]
|
||||
- name: stur # JL: assumed from n1 opt guide
|
||||
operands:
|
||||
- class: register
|
||||
prefix: q
|
||||
- class: memory
|
||||
base: x
|
||||
offset: '*'
|
||||
index: '*'
|
||||
scale: '*'
|
||||
pre-indexed: false
|
||||
post-indexed: false
|
||||
throughput: 1.0
|
||||
latency: 0 # 2*p67+1*p45
|
||||
port_pressure: [[2, '67'], [1, '45']]
|
||||
- name: str
|
||||
operands:
|
||||
- class: register
|
||||
prefix: x
|
||||
- class: memory
|
||||
base: x
|
||||
offset: '*'
|
||||
index: '*'
|
||||
scale: '*'
|
||||
pre-indexed: false
|
||||
post-indexed: false
|
||||
throughput: 0.5
|
||||
latency: 0 # 1*p67+1*p23
|
||||
port_pressure: [[1, '56'], [1, '23']]
|
||||
- name: str
|
||||
operands:
|
||||
- class: register
|
||||
prefix: d
|
||||
- class: memory
|
||||
base: x
|
||||
offset: '*'
|
||||
index: '*'
|
||||
scale: '*'
|
||||
pre-indexed: false
|
||||
post-indexed: false
|
||||
throughput: 0.5
|
||||
latency: 0 # 1*p67+1*p45
|
||||
port_pressure: [[1, '67'], [1, '45']]
|
||||
- name: str
|
||||
operands:
|
||||
- class: register
|
||||
prefix: d
|
||||
- class: memory
|
||||
base: x
|
||||
offset: '*'
|
||||
index: '*'
|
||||
scale: '*'
|
||||
pre-indexed: false
|
||||
post-indexed: true
|
||||
throughput: 0.5
|
||||
latency: 0 # 1*p67+1*p45+1*p123
|
||||
port_pressure: [[1, '67'], [1, '45'], [1, '123']]
|
||||
- name: str
|
||||
operands:
|
||||
- class: register
|
||||
prefix: q
|
||||
- class: memory
|
||||
base: x
|
||||
offset: '*'
|
||||
index: '*'
|
||||
scale: 1
|
||||
pre-indexed: false
|
||||
post-indexed: false
|
||||
throughput: 1.0
|
||||
latency: 0 # 2*p67+1*p45
|
||||
port_pressure: [[1, '67'], [1, '45']]
|
||||
- name: str
|
||||
operands:
|
||||
- class: register
|
||||
prefix: q
|
||||
- class: memory
|
||||
base: x
|
||||
offset: '*'
|
||||
index: '*'
|
||||
scale: '*'
|
||||
pre-indexed: false
|
||||
post-indexed: true
|
||||
throughput: 1.0
|
||||
latency: 0 # 1*p67+1*p45+1*123
|
||||
port_pressure: [[1, '67'], [1, '45'], [1, '123']]
|
||||
- name: str
|
||||
operands:
|
||||
- class: register
|
||||
prefix: x
|
||||
- class: memory
|
||||
base: x
|
||||
offset: '*'
|
||||
index: '*'
|
||||
scale: '*'
|
||||
pre-indexed: false
|
||||
post-indexed: true
|
||||
throughput: 1.0
|
||||
latency: 0 # 1*p67+1*p23+1*p123
|
||||
port_pressure: [[1, '67'], [1, '23'], [1, '123']]
|
||||
- name: sub
|
||||
operands:
|
||||
- class: register
|
||||
prefix: w
|
||||
- class: register
|
||||
prefix: w
|
||||
- class: immediate
|
||||
imd: int
|
||||
throughput: 0.33333333
|
||||
latency: 1.0 # 1*p123
|
||||
port_pressure: [[1, '123']]
|
||||
@@ -17,7 +17,7 @@ MODULE_DATA_DIR = os.path.join(
|
||||
)
|
||||
LOCAL_OSACA_DIR = os.path.join(os.path.expanduser('~') + '/.osaca/')
|
||||
DATA_DIR = os.path.join(LOCAL_OSACA_DIR, 'data/')
|
||||
SUPPORTED_ARCHS = ['SNB', 'IVB', 'HSW', 'BDW', 'SKX', 'CSX', 'ZEN1', 'ZEN2', 'TX2']
|
||||
SUPPORTED_ARCHS = ['SNB', 'IVB', 'HSW', 'BDW', 'SKX', 'CSX', 'ZEN1', 'ZEN2', 'TX2', 'N1']
|
||||
|
||||
|
||||
# Stolen from pip
|
||||
@@ -71,7 +71,7 @@ def create_parser(parser=None):
|
||||
parser.add_argument(
|
||||
'--arch',
|
||||
type=str,
|
||||
help='Define architecture (SNB, IVB, HSW, BDW, SKX, CSX, ZEN1, ZEN2, TX2).',
|
||||
help='Define architecture (SNB, IVB, HSW, BDW, SKX, CSX, ZEN1, ZEN2, TX2, N1).',
|
||||
)
|
||||
parser.add_argument(
|
||||
'--fixed',
|
||||
|
||||
@@ -241,6 +241,7 @@ class MachineModel(object):
|
||||
"""Return ISA for given micro-arch ``arch``."""
|
||||
arch_dict = {
|
||||
'tx2': 'aarch64',
|
||||
'n1': 'aarch64',
|
||||
'zen1': 'x86',
|
||||
'zen+': 'x86',
|
||||
'zen2': 'x86',
|
||||
|
||||
Reference in New Issue
Block a user