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added default load TP and relocation in identifier

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JanLJL
2019-12-18 16:56:20 +01:00
parent d88617109f
commit bbb004a2aa
12 changed files with 25 additions and 3 deletions
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5
osaca/semantics/arch_semantics.py
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@@ -249,7 +249,10 @@ class ArchSemantics(ISASemantics):
def convert_mem_to_reg(self, memory, reg_type, reg_id='0'):
if self._isa == 'x86':
register = {'register': {'name': reg_type + reg_id}}
if reg_type == 'gpr':
register = {'register': {'name': 'r' + str(int(reg_id) + 9)}}
else:
register = {'register': {'name': reg_type + reg_id}}
elif self._isa == 'aarch64':
register = {'register': {'prefix': reg_type, 'name': reg_id}}
return register