added lane comparison for AArch64 reg operands

2026-01-06 11:10:06 +01:00 · 2022-01-26 14:24:48 +01:00
parent c917a83974
commit d2a4749c39
1 changed files with 6 additions and 0 deletions
--- a/osaca/semantics/hw_model.py
+++ b/osaca/semantics/hw_model.py
@@ -639,6 +639,12 @@ class MachineModel(object):
            ):
                return True
            return False
+        if "lanes" in reg:
+            if "lanes" in i_reg and (
+                reg["lanes"] == i_reg["lanes"] or self.WILDCARD in (reg["lanes"] + i_reg["lanes"])
+            ):
+                return True
+            return False
        return True

    def _is_x86_reg_type(self, i_reg, reg, consider_masking=False):