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https://github.com/RRZE-HPC/OSACA.git
synced 2025-12-13 07:30:06 +01:00
Rewrite the parsing of register expressions. GCC, for reasons unknown, put the displacement in the middle.
I am completely restructuring the parser definition so that they are more explicit. They are more verbose too, but at least I understand what they do.
This commit is contained in:
pleroy
@@ -318,28 +318,45 @@ class ParserX86Intel(ParserX86):
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base_register = self.register
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index_register = self.register
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scale = pp.Word("1248", exact=1)
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post_displacement = pp.Group(
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(pp.Literal("+") ^ pp.Literal("-")).setResultsName("sign") + integer_number
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| identifier
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).setResultsName(self.immediate_id)
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pre_displacement = pp.Group(integer_number + pp.Literal("+")).setResultsName(
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self.immediate_id
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base = base_register.setResultsName("base")
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displacement = pp.Group(
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pp.Group(
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integer_number ^ identifier
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).setResultsName(self.immediate_id)
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).setResultsName("displacement")
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short_indexed = index_register.setResultsName("index")
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long_indexed = (
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index_register.setResultsName("index")
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+ pp.Literal("*")
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+ scale.setResultsName("scale")
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)
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indexed = pp.Group(
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index_register.setResultsName("index")
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+ pp.Optional(pp.Literal("*") + scale.setResultsName("scale"))
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short_indexed
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^ long_indexed
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).setResultsName("indexed")
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operator = pp.Word("+-", exact=1)
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# Syntax:
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# `base` always preceedes `indexed`.
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# `short_indexed` is only allowed if it follows `base`, not alone.
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# `displacement` can go anywhere.
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# It's easier to list all the alternatives than to represent these rules using complicated
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# `Optional` and what not.
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register_expression = pp.Group(
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pp.Literal("[")
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+ pp.Optional(pp.Group(pre_displacement).setResultsName("pre_displacement"))
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+ pp.Group(
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base_register.setResultsName("base")
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^ pp.Group(
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base_register.setResultsName("base") + pp.Literal("+") + indexed
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).setResultsName("base_and_indexed")
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^ indexed
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).setResultsName("non_displacement")
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+ pp.Optional(pp.Group(post_displacement).setResultsName("post_displacement"))
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+ (
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base
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^ (base + operator + displacement)
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^ (base + operator + displacement + operator + indexed)
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^ (base + operator + indexed)
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^ (base + operator + indexed + operator + displacement)
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^ (displacement + operator + base)
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^ (displacement + operator + base + operator + indexed)
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^ (displacement + operator + pp.Group(long_indexed).setResultsName("indexed"))
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^ pp.Group(long_indexed).setResultsName("indexed")
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^ (pp.Group(long_indexed).setResultsName("indexed") + operator + displacement)
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)
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+ pp.Literal("]")
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).setResultsName("register_expression")
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@@ -640,33 +657,16 @@ class ParserX86Intel(ParserX86):
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return RegisterOperand(name=operand.name)
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def process_register_expression(self, register_expression):
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pre_displacement = register_expression.get("pre_displacement")
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post_displacement = register_expression.get("post_displacement")
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non_displacement = register_expression.get("non_displacement")
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base = None
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indexed = None
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if non_displacement:
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base_and_indexed = non_displacement.get("base_and_indexed")
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if base_and_indexed:
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base = base_and_indexed.get("base")
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indexed = base_and_indexed.get("indexed")
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else:
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base = non_displacement.get("base")
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if not base:
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indexed = non_displacement.get("indexed")
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base = register_expression.get("base")
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displacement = register_expression.get("displacement")
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indexed = register_expression.get("indexed")
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index = None
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scale = 1
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if indexed:
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index = indexed.get("index")
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scale = int(indexed.get("scale", "1"), 0)
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else:
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index = None
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scale = 1
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displacement_op = (
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self.process_immediate(pre_displacement.immediate) if pre_displacement else None
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)
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displacement_op = (
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self.process_immediate(post_displacement.immediate)
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if post_displacement
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else displacement_op
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self.process_immediate(displacement.immediate) if displacement else None
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)
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base_op = RegisterOperand(name=base.name) if base else None
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index_op = RegisterOperand(name=index.name) if index else None
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102
tests/test_files/gs_x86_gcc.s
Normal file
102
tests/test_files/gs_x86_gcc.s
Normal file
@@ -0,0 +1,102 @@
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# Produced with gcc 14.2 with -O3 -march=sapphirerapids -fopenmp-simd -mprefer-vector-width=512, https://godbolt.org/z/drE47x1b4.
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.LC3:
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.string "%f\n"
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main:
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push r14
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xor edi, edi
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push r13
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push r12
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push rbp
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push rbx
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call time
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mov edi, eax
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call srand
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mov edi, 1600
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call malloc
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mov r12, rax
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mov rbp, rax
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lea r13, [rax+1600]
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mov rbx, rax
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.L2:
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mov edi, 1600
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add rbx, 8
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call malloc
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mov QWORD PTR [rbx-8], rax
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cmp r13, rbx
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jne .L2
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lea rbx, [r12+8]
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lea r13, [r12+1592]
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.L5:
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mov r14d, 8
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.L4:
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call rand
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vxorpd xmm2, xmm2, xmm2
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mov rcx, QWORD PTR [rbx]
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movsx rdx, eax
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mov esi, eax
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imul rdx, rdx, 351843721
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sar esi, 31
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sar rdx, 45
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sub edx, esi
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imul edx, edx, 100000
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sub eax, edx
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vcvtsi2sd xmm0, xmm2, eax
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vdivsd xmm0, xmm0, QWORD PTR .LC0[rip]
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vmovsd QWORD PTR [rcx+r14], xmm0
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add r14, 8
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cmp r14, 1592
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jne .L4
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add rbx, 8
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cmp r13, rbx
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jne .L5
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vmovsd xmm1, QWORD PTR .LC1[rip]
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lea rdi, [r12+1584]
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.L6:
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mov rdx, QWORD PTR [rbp+8]
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mov rcx, QWORD PTR [rbp+16]
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mov eax, 1
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mov rsi, QWORD PTR [rbp+0]
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vmovsd xmm0, QWORD PTR [rdx]
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.L7:
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vaddsd xmm0, xmm0, QWORD PTR [rcx+rax*8]
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vaddsd xmm0, xmm0, QWORD PTR [rdx+8+rax*8]
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vaddsd xmm0, xmm0, QWORD PTR [rsi+rax*8]
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vmulsd xmm0, xmm0, xmm1
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vmovsd QWORD PTR [rdx+rax*8], xmm0
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inc rax
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cmp rax, 199
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jne .L7
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vmovsd xmm0, QWORD PTR [rdx+1592]
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add rbp, 8
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vmovsd QWORD PTR [rcx+8], xmm0
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cmp rdi, rbp
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jne .L6
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mov rax, QWORD PTR [r12+1584]
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vmovsd xmm0, QWORD PTR .LC2[rip]
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vucomisd xmm0, QWORD PTR [rax+1584]
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jp .L9
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je .L19
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.L9:
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pop rbx
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xor eax, eax
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pop rbp
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pop r12
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pop r13
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pop r14
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ret
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.L19:
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mov rax, QWORD PTR [r12]
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mov edi, OFFSET FLAT:.LC3
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vmovsd xmm0, QWORD PTR [rax]
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mov eax, 1
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call printf
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jmp .L9
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.LC0:
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.long 0
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.long 1083129856
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.LC1:
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.long 2061584302
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.long 1072934420
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.LC2:
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.long -57724360
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.long 1072939201
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@@ -25,6 +25,8 @@ class TestParserX86Intel(unittest.TestCase):
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self.triad_iaca_code = f.read()
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with open(self._find_file("gs_x86_icc.s")) as f:
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self.gs_icc_code = f.read()
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with open(self._find_file("gs_x86_gcc.s")) as f:
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self.gs_gcc_code = f.read()
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##################
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# Test
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@@ -100,6 +102,7 @@ class TestParserX86Intel(unittest.TestCase):
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instr11 = "\tlea\trcx, OFFSET FLAT:??_R0N@8+8"
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instr12 = "\tvfmadd213sd xmm0, xmm1, QWORD PTR __real@bfc5555555555555"
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instr13 = "\tjmp\t$LN18@operator"
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instr14 = "vaddsd xmm0, xmm0, QWORD PTR [rdx+8+rax*8]"
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parsed_1 = self.parser.parse_instruction(instr1)
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parsed_2 = self.parser.parse_instruction(instr2)
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@@ -114,6 +117,7 @@ class TestParserX86Intel(unittest.TestCase):
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parsed_11 = self.parser.parse_instruction(instr11)
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parsed_12 = self.parser.parse_instruction(instr12)
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parsed_13 = self.parser.parse_instruction(instr13)
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parsed_14 = self.parser.parse_instruction(instr14)
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self.assertEqual(parsed_1.mnemonic, "sub")
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self.assertEqual(parsed_1.operands[0], RegisterOperand(name="RSP"))
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@@ -204,6 +208,17 @@ class TestParserX86Intel(unittest.TestCase):
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self.assertEqual(parsed_13.mnemonic, "jmp")
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self.assertEqual(parsed_13.operands[0], IdentifierOperand(name="$LN18@operator"))
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self.assertEqual(parsed_14.mnemonic, "vaddsd")
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self.assertEqual(parsed_14.operands[0],
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RegisterOperand(name="XMM0"))
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self.assertEqual(parsed_14.operands[1],
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RegisterOperand(name="XMM0"))
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self.assertEqual(parsed_14.operands[2],
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MemoryOperand(base=RegisterOperand(name="RDX"),
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offset=ImmediateOperand(value=8),
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index=RegisterOperand(name="RAX"),
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scale=8))
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def test_parse_line(self):
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line_comment = "; -- Begin main"
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line_instruction = "\tret\t0"
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@@ -344,6 +359,27 @@ class TestParserX86Intel(unittest.TestCase):
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)
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self.assertEqual(len(parsed), 227)
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def test_parse_file4(self):
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parsed = self.parser.parse_file(self.gs_gcc_code)
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self.assertEqual(parsed[0].line_number, 1)
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# Check a few lines to make sure that we produced something reasonable.
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self.assertEqual(parsed[61],
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InstructionForm(mnemonic="vaddsd",
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operands=[RegisterOperand("XMM0"),
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RegisterOperand("XMM0"),
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MemoryOperand(base=RegisterOperand("RDX"),
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index=RegisterOperand("RAX"),
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scale=8,
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offset=ImmediateOperand(value=8))],
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line=" vaddsd xmm0, xmm0, QWORD PTR [rdx+8+rax*8]",
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line_number=62))
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self.assertEqual(parsed[101],
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InstructionForm(directive_id=DirectiveOperand(name=".long",
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parameters=["1072939201"]),
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line=" .long 1072939201",
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line_number=102))
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self.assertEqual(len(parsed), 102)
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def test_normalize_imd(self):
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imd_binary = ImmediateOperand(value="1001111B")
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imd_octal = ImmediateOperand(value="117O")
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